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rdc ? risc dsp controller r88 30 lv rdc semiconductor co. rev :1.0 subject to change without notice 1 R8830LV 16-bit risc microcontroller user ? s manual rdc risc dsp controller rdc semiconductor co., ltd http:\\www.rdc.com.tw tel. 886-3-583-2666 fax 886-3-583-2688
rdc ? risc dsp controller r88 30 lv rdc semiconductor co. rev :1.0 subject to change without notice 2 contents -------------------------------- -------------------------------- ---------------- page 1. features -------------------------------- -------------------------------- --------- 4 2. block diagram -------------------------------- -------------------------------- 4 3. pin configuration -------------------------------- ----------------------------- 5 4. pin description -------------------------------- -------------------------------- 8 5. basic application system block -------------------------------- ------------ 14 6. oscillator characteristics -------------------------------- ------------------ 15 7. read/write timing diagram -------------------------------- ---------------- 16 8. execution unit -------------------------------- ----------------------------- 18 8.1 general register -------------------------------- ------------------------- 18 8.2 segment register -------------------------------- ------------------------- 18 8.3 instruction pointer and status flags register ----------------------------- 19 8.4 address generation -------------------------------- ---------------------- 20 9. peripheral control block register -------------------------------- -------- 21 10. system clock block -------------------------------- ------------------------ 23 11. reset -------------------------------- -------------------------------- ---------- 24 12. bus interface unit -------------------------------- --------------------------- 26 12.1 memory and i/o interface -------------------------------- ------------------- 26 12.2 data bus -------------------------------- -------------------------------- - 26 12.3 wait states -------------------------------- -------------------------------- ------- 27 12.4 bus hold -------------------------------- -------------------------------- ---------- 28 13. chip select unit -------------------------------- ---------------------------- 30 13.1 ucs -------------------------------- -------------------------------- -------------- 30 13.2 lcs -------------------------------- -------------------------------- -------------- 31 13.3 mcsx -------------------------------- -------------------------------- ----------- 33 13.4 pcsx -------------------------------- -------------------------------- ------------ 34 14. interrupt controller unit -------------------------------- ----------------- 37 14.1 master mode and slave mode -------------------------------- --------- 37 14.2 interrupt vector, type -------------------------------- ------------------------ 38 14.3 interrupt request -------------------------------- ---------------------- 39 14.4 interrupt acknowledge -------------------------------- ---------------- 39 14.5 programming register -------------------------------- ----------------------- 40
rdc ? risc dsp controller r88 30 lv rdc semiconductor co. rev :1.0 subject to change without notice 3 15. dma unit -------------------------------- -------------------------------- ---- 53 15.1 dma operation -------------------------------- -------------------------------- 53 15.2 external request -------------------------------- ------------------------------- 58 15.3 serial port dma/transfer -------------------------------- ----------- 59 16. timer control unit -------------------------------- ------------------------ 61 16.1 timer/counter unit output mode -------------------------------- -- 65 17. watchdog timer -------------------------------- ---------------------------- 66 18. asynchronous serial port -------------------------------- ----------------- 69 18.1 serial port flow control -------------------------------- ----------- 69 18.1.1 dce/dte protocol -------------------------------- --------- 69 18.1.2 cts/rtr protocol -------------------------------- ---------- 70 18.2 dma transfer to/form a serial port function ------------------ 70 18.3 the asynchronous modes description -------------------------- 71 19. pio unit -------------------------------- -------------------------------- ----- 76 19.1 pio multi-function pin list table -------------------------------- --- 76 20. psram control unit -------------------------------- ---------------------- 79 21. instruction set opcodes and clock cycle ------------------------------ 80 21.1 R8830LV execution timings -------------------------------- --------- 84 22. dc characteristics -------------------------------- ------------------------- 85 23. ac characteristics -------------------------------- ------------------------- 86 24. package information -------------------------------- ---------------------- 95
rdc ? risc dsp controller r88 30 lv rdc semiconductor co. rev :1.0 subject to change without notice 4 16-bit microcontroller with 8-bit external data bus 1. features l risc architecture l static design & synthesizable design l bus interface - multiplexed address and data bus which compatible with 80c188 microprocessor - supports nonmultiplexed address bus [ a19 : a0] - 1m byte memory address space - 64k byte i/o space l software compatible with the 80c186 l support two asynchronous serial channel with hardware handshaking signals. l support serial port with dma transfers l supports 32 pio pins l psram (pseudo static ram) interface with auto-refresh control l three independent 16-bit timers and one independent watchdog timer l the interrupt controller with seven maskable external interrupts and one nonmaskable external interrupt l two independent dma channels l programmable chip-select logic for memory or i/o bus cycle decoder l programmable wait-state generator 2. block diagram dma unit psram control unit chip select unit refresh control unit bus interface unit pio unit timer control unit interrupt control unit clock and power management asynchro- nous serial port0 instruction queue (64bits) instruction decoder register file general, segment, eflag register alu (special, logic, adder, bsf) micro rom ea / la address control signal execution unit x1 x2 clkouta clkoutb int6-int4 int0 tmrin0 tmrout0 tmrin1 tmrout1 drq0 drq1 txd0 rxd0 a19~a0 ad7~ad0 ao15~ao8 rd vcc gnd lcs/once0 mcs3/rfsh ucs/once1 pcs5/a1 pcs6/a2 ardy srdy s2~s0 dt/r den hold hlda s6/clkdiv2 uzi ale asynchro- nous serial port1 rts0/rtr0 cts0/enrx0 txd1 rxd1 rts1/rtr1 cts1/enrx1 rfsh2/aden wr wb int3/inta1/irq int2/inta0 int1/select nmi rst mcs2-mcs0 pcs3-pcs0
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 5 3. pin configuration (pqfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 R8830LV microcontroller rxd0/pio23 txd0/pio22 ale ardy gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 vcc a0 gnd gnd hlda hold srdy/pio6 nmi int4/pio30 int0 vcc gnd vcc gnd tmrin1/pio0 tmrout1/pio1 tmrout0/pio10 tmrin0/pio11 drq1/int5/pio13 drq0/int6/pio12 ad0 ao8 ad1 ao9 ad2 ao10 ad3 a011 ad4 ao12 ad5 gnd ao13 ad6 vcc ao14 ad7 ao15 txd1/pio27 rxd1/pio28 int3/inta1/irq ucs/once1 lcs/once0 s6/clkdiv2/pio29 dt/r/pio4 den/pio5 mcs0/pio14 mcs1/pio15 int2/inta0/pio31 pcs6/a2/pio2 pcs5/a1/pio3 pcs1/pio17 pcs0/pio16 mcs2/pio24 mcs3/rfsh/pio25 rst uzi/pio26 wr rd s2 s1 s0 int1/select pcs2/cts1/enrx1/pio18 pcs3/rts1/rtr1/pio19 rts0/rtr0/pio20 cts0/enrx0/pio21 wb rfsh2/aden
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 6 (lqfp) R8830LV ad0 ao8 ad1 ao9 ad2 ao10 ad3 ao11 ad4 ao12 ad5 gnd ao13 ad6 vcc ao14 ad7 ao15 s6/clkdiv2/pio29 uzi/pio26 txd1/pio27 rxd1/pio28 rxd0/pio23 txd0/pio22 wr rd ale ardy s1 s0 gnd x1 x2 vcc clkouta clkoutb gnd a19/pio9 a18/pio8 vcc a17/pio7 a16 a15 a14 a13 a12 a11 a9 a10 a8 a7 a6 a4 a5 a3 a2 vcc a0 a1 gnd hold hlda srdy/pio6 nmi int4/pio30 int0 vcc gnd vcc gnd tmrin1/pio0 tmrout0/pio10 tmrin0/pio11 tmrout1/pio1 drq1/int5/pio13 drq0/int6/pio12 dt/r/pio4 int3/inta1/irq int2/inta0/pio31 int1/select lcs/once0 pcs6/a2/pio2 pcs5/a1/pio3 pcs1/pio17 pcs0/pio16 rst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 55 54 53 52 51 60 59 58 57 56 65 64 63 62 61 70 69 68 67 66 75 74 73 72 71 76 77 78 80 79 81 82 83 85 84 86 87 88 90 89 91 92 93 95 94 96 97 98 100 99 den/pio5 mcs3/rfsh/pio25 cts0/enrx0/pio21 rts0/rtr0/pio20 gnd pcs3/rts1/rtr1/pio19 pcs2/cts1/enrx1/pio18 rfsh2/aden s2 wb mcs0/pio14 mcs1/pio15 ucs/once1 mcs2/pio24
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 7 R8830LV pin out table pin name lqfp pin no. pqfp pin no. pin name lqfp pin no. pqfp pin no. ad0 1 78 a11 51 28 ao8 2 79 a10 52 29 ad1 3 80 a9 53 30 ao9 4 81 a8 54 31 ad2 5 82 a7 55 32 ao10 6 83 a6 56 33 ad3 7 84 a5 57 34 ao11 8 85 a4 58 35 ad4 9 86 a3 59 36 ao12 10 87 a2 60 37 ad5 11 88 vcc 61 38 gnd 12 89 a1 62 39 ao13 13 90 a0 63 40 ad6 14 91 gnd 64 41 vcc 15 92 gnd 65 42 ao14 16 93 wb 66 43 ad7 17 94 hlda 67 44 ao15 18 95 hold 68 45 s6/ 2 clkdiv /pi o29 19 96 srdy/pi o6 69 46 uzi /pi o26 20 97 nmi 70 47 txd1/pi o27 21 98 dt/ r /pi o4 71 48 rxd1/pi o28 22 99 den /pi o5 72 49 0 cts / 0 enrx /pio21 23 100 0 mcs /pi o14 73 50 rxd0/pi o23 24 1 1 mcs /pi o15 74 51 txd0/pi o22 25 2 i nt4/ pi o30 75 52 0 rts / 0 rtr /pio20 26 3 i nt3/ 1 inta /i rq 76 53 2 rfsh / aden 27 4 i nt2/ 0 inta /pi o31 77 54 wr 28 5 i nt1/ select 78 55 rd 29 6 i nt0 79 56 ale 30 7 ucs / 1 once 80 57 ardy 31 8 lcs / 0 once 81 58 2 s 32 9 6 pcs /a2/pi o2 82 59 1 s 33 10 5 pcs /a1/pi o3 83 60 0 s 34 11 vcc 84 31 gnd 35 12 3 pcs / 1 rts / 1 rtr /pi o19 85 62 x1 36 13 2 pcs / 1 cts / 1 enrx /pi o18 86 63 x2 37 14 gnd 87 64 vcc 38 15 1 pcs /pi o17 88 65 clkouta 39 16 0 pcs /pi o16 89 66 clkoutb 40 17 vcc 90 67 gnd 41 18 2 mcs /pi o24 91 68 a19/pi o9 42 19 3 mcs / rfsh /pi o25 92 69 a18/pi o8 43 20 gnd 93 70 vcc 44 21 rst 94 71 a17/pi o7 45 22 tmri n1/pi o0 95 72 a16 46 23 tmrout1/pi o1 96 73 a15 47 24 tmrout0/pi o10 97 74 a14 48 25 tmri n0/pi o11 98 75 a13 49 26 drq1/int6/pi o13 99 76 a12 50 27 drq0/int5/pi o12 100 77
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 8 4. pin description pin no.(pqfp) symbol type description 15, 21, 38, 61, 67, 92 vcc input system power: +5 volt power supply. 12, 18, 41, 42 64, 70, 89 gnd input system ground. 71 rst input* reset input. when rst is asserted, the cpu immediately terminate all operation, clears the internal registers & logic, and the address transfers to the reset address ffff0h. 13 x1 input input to the oscillator amplifier. 14 x2 output output from the inverting oscillator amplifier. 16 clkouta output clock output a. the clkouta operation is the same as crystal input frequency (x1). clkouta remains active during reset and bus hold conditions. 17 clkoutb output clock output b. the clkoutb operation is the same as crystal input frequency (x1). clkoutb remains active during reset and bus hold conditions. asynchronous serial port interface 1 rxd0/pio23 input/output receive data for asynchronous serial port 0. this pin receives asynchronous serial data. 2 txd0/pio22 output/input tranmit data for asynchronous serial port 0. this pin transmits asynchronous serial data from the uart of the microcontrolles. 3 0 rts / 0 rtr /pio20 output/input ready to send/ready to receive signal for asynchronous serial port 0. when the 0 rts bit in auxcon register is set and fc bit in the serial port 0 register is set the 0 rts signal is enabled. other the 0 rts bit is cleared and fc bit is set the 0 rtr signal is enabled. 100 0 cts / 0 enrx /pio21 input/output clear to send/enable receiver request signal for asyncgronous serial port 0. when 0 enrx bit in the auxcon register is cleared and the fc bit in the serial port 0 control register is set the 0 cts signal is enabled. otherwise when 0 enrx bit is set and the fc bit is set the 0 enrx signal is enabled. 98 txd1/pio27 output/input tranmit data for asynchronous serial port 0. this pin transmits asynchronous serial data from the uart of the microcontrolles. 99 rxd1/pio28 input/output receive data for asynchronous serial port 0. this pin receives asynchronous serial data. 62 3 pcs / 1 rts / 1 rtr output/input ready to send/ready to receive signal for asynchronous serial port 1. when the 1 rts bit in auxcon register is set and fc bit in the serial port 1 register is set the 1 rts signal is enabled. otherwise the 1 rts bit is cleared and fc bit is set the 1 rtr signal is enabled.
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 9 63 2 pcs / 1 cts / 1 enrx output/input clear to send/enable receiver request signal for asynchronous serial port 0. when 1 enrx bit in the auxcon register is cleared and the fc bit in the serial port 0 control register is set the 1 cts signal is enabled. otherwise when 1 enrx bit is set and the fc bit is set the 1 enrx signal is enabled. bus interface 4 2 rfsh / aden output/input for 2 rfsh feature, this pin actice low to indicate a dram refresh bus cycle. for aden feature, when this pin is held high on power-on reset the address portion of the ad bus can be disabled or enabled by da bit in the lmcs and umcs register during lcs or ucs bus cycle access. the 2 rfsh / aden with a internal weak pull-up resister, so no external pull-up resister is reqired. the ad bus always drives both address and data during lcs or ucs bus cycle access, if the 2 rfsh / aden pin with external pull-low resister during reset. 5 wr output write strobe. this pin indicates that the data on the bus is to be written into a memory or an i/o device. wr is active during t2, t3 and tw of any write cycle, floats during a bus hold or reset. 6 rd output read strobe. active low signal which indicates that the microcontroller is performing a memory or i/o read cycle. rd floats during bus hold or reset. 7 ale output address latch enable. active high. this pin indicates that an address output on the ad bus. address is guaranteed to be valid on the trailing edge of ale. this pin is tri-stated during once mode and is never floating during a bus hold or reset. 8 ardy input asynchronous ready. this pin performs the microcontroller that the address memory space or i/o device will complete a data transfer. the ardy pin accepts a rising edge that is asynchronous to clkouta and is active high. the falling edge of ardy must be synchronized to clkouta. tie ardy high, the microcontroller is always asserted in the ready condition. if the ardy is not used, tie this pin low to yield control to srdy. bus cycle status. these pins are encoded to indicate the bus status. 2 s can be used as memory or i/o indicator. 1 s can be used as dt/ r indicator. these pins are floating during hold and reset. bus cycle encoding description 2 s 1 s 0 s bus cycle 9 10 11 2 s 1 s 0 s output 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 interrupt acknowledge read data from i/o write data to i/o halt instruction fetch read data from memory write data to memory passive
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 10 19 20 22 23-37 39, 40 a19/pio9 a18/pio8 a17/pio7 a16-a2 a1 , a0 output/input address bus. non-multiplex memory or i/o address. the a bus is one-half of a clkouta period earlier than the ad bus. these pins are high-impedance during bus hold or reset. 78,80,82,84, 86, 88,91,94 ad0-ad7 input/output the multiplexed address and data bus for memory or i/o accessing. the address is present during the t1 clock phase, and the data bus phase is in t2-t4 cycle. the address phase of the ad bus can be disabled when the bhe / aden pin with external pull-low resister during reset. the ad bus is in high-impedance state during bus hold or reset condition and this bus also be used to load system configuration information (with pull-up or pull-low resister) into the rescon(f6h) register when the reset input from low go high. 79,81,83,85,8 7,90 93,95 ao8-ao15 output address only bus, in the multiplexed address bus, the ao15 ? ao8 combine with the ad7 ? ad0 to form a 16 bit address bus. these pins are floating during a bus hold or reset. 43 wb output write byte. this pin active low to indicate a write cycle on the bus. it is floating during reset. 44 hlda output bus hold acknowledge. active high. the microcontroller will issue a hlda in response to a hold request by external bus master at the end of t4 or ti. when the microcontroller is in hold status (hlda is high), the ad15-d0, a19-a0, wr , rd , den , 0 s - 1 s , 6 s , bhe , dt/ r , whb and wlb are floating, and the ucs , lcs , 6 pcs - 5 pcs , 3 mcs - 0 mcs and 3 pcs - 0 pcs will be drive high. after hold is detected as being low, the microcontroller will lower hlda. 45 hold input bus hold request. active high. this pin indicates that another bus master is requesting the local bus. 46 srdy/pio6 input/output synchronous ready. this pin performs the microcontroller that the address memory space or i/o device will complete a data transfer. the srdy pin accepts a falling edge that is asynchronous to clkouta and is active high. srdy is accomplished by elimination of the one-half clock period required to internally synchronize ardy. tie srdy high the microcontroller is always assert in the ready condition. if the srdy is not used, tie this pin low to yield control to ardy. 48 dt/ r /pio4 output/input data transmit or receive. this pin indicates the direction of data flow through an external data-bus transceiver. dt/ r low, the microcontroller receives data. when dt/r is asserted high, the microcontroller writes data to the data bus. 49 den /pio5 output/input data enable. this pin is provided as a data bus transceiver output enable. den is asserted during memory and i/o access. den is drived high when dt/ r changes state. it is floating during bus hold or reset condition. 96 s6/ 2 clkdiv /pio29 output/input bus cycle status bit6/clock divided by 2. for s6 feature, this pin is low to indicate a microcontroller-initiated bus cycle or high to indicate a dma-initiated bus cycle during t2, t3, tw and t4. for 2 clkdiv feature. the internal clock of microcontroller is the external clock be divided by 2. (clkouta, clkoutb=x1/2), if this pin held low during power-on reset. the pin is sampled on the rising edge of
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 11 rst . 97 uzi /pio26 output/input upper zero indicate. this pin is the logical or of the inverted a19-a16. it asserts in the t1 and is held throughout the cycle. chip select unit interface 50 51 68 69 0 mcs /pio14 1 mcs /pio15 2 mcs /pio24 3 mcs / rfsh /pio25 output/input midrange memory chip selects. for mcs feature, these pins are active low when enable the mmcs(a6h) register to access a memory. the address ranges are programmable. 3 mcs - 0 mcs are held high during bus hold. when programming lmcs(a2h) register, pin69 is as a rfsh pin to auto refresh the psram. 57 ucs / 1 once output/input upper memory chip select/once mode request 1. for ucs feature, this pin acts low when system accesses the defined portion memory block of the upper 512k bytes (80000h- fffffh) memory region. ucs default acted address region is from f0000h to fffffh after power-on reset. the address range acting ucs is programmed by software. for 1 once feature. if 0 once and 1 once are sampled low on the rising edge of rst . the microcontroller enters once mode. in once mode, all pins are high-impedance. this pin incorporates weakly pull-up resistor. 58 lcs / 0 once output/input lower memory chip select/once mode request 0. for lcs feature, this pin acts low when the microcontroller accesses the defined portion memory block of the lower 512k (00000h- 7ffffh ) memory region. the address range acting lcs is programmed by software. for 0 once feature, see ucs / 1 once description. this pin incorporates weakly pull-up register. 59 60 6 pcs /a2/pio2 5 pcs /a1/pio3 output/input peripheral chip selects/latched address bit. for pcs feature, these pins act low when the microcontroller accesses the fifth or sixth region of the peripheral memory (i/o or memory space). the base address of pcs is programmable. these pins assert with the ad address bus and are not float during bus hold. for latched address bit feature. these pins output the latched address a2, a1 when cleared the ex bit in the mcs and pcs auxiliary register. the a2, a1 retains previous latched data during bus hold. 62 63 65 66 3 pcs / 1 rts / 1 rtr /pio19 2 pcs / 1 cts / 1 enrx pio18 1 pcs /pio17 0 pcs /pio16 output/input peripheral chip selects. these pins act low when the microcontroller accesses the defined memory area of the peripheral memory block (i/o or memory address). for i/o accessed, the base address can be programmed in the region 00000h to 0ffffh. for memory address access, the base address can be located in the 1m byte memory address region. these pins assert with the multiplexed ad address bus and are not float during bus hold. interrupt control unit interface 47 nmi input nonmaskable interrupt. the nmi is the highest priority hardware interrupt and is nonmaskable. when this pin is asserted (nmi transition from low to high), the microcontroller always transfers the address bus to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 12 vector table. the nmi pin must be asserted for at least one clkouta period to guarantee that the interrupt is recognized. 52 int4/pio30 input/output maskable interrupt request 4. act high. this pin indicates that an interrupt request has occurred. the microcontroller will jump to the int4 address vector to execute the service routine if the int4 is enable. the interrupt input can be configured to be either edge- or level-triggered. the requesting device must holt the int4 until the request is acknowledged to guarantee interrupt recognition. 53 int3/ 1 inta /irq input/output maskable interrupt request 3/interrupt acknowledge 1/slave interrupt request. for int3 feature, except the difference interrupt line and interrupt address vector, the function of int3 is the same as int4. for 1 inta feature, in cascade mode or special fully-nested mode, this pin corresponds the int1. for irq feature, when the microcontroller is as a slave device, this pin issues an interrupt request to the master interrupt controller. 54 int2/ 0 inta /pio31 input/output maskable interrupt request 2/interrupt acknowledge 0. for int2 feature, except the difference interrupt line and interrupt address vector, the function of int2 is the same as int4. for 0 inta feature, in cascade mode or special fully-nested mode, this pin corresponds the int0. 55 int1/ select input/output maskable interrupt request 1/slave select. for int1 feature, except the difference interrupt line and interrupt address vector, the function of int1 is the same as int4. for select feature, when the microcontroller is as a slave device, this pin is drived from the master interrupt controller decoding. this pin acts to indicate that an interrupt appears on the address and data bus. the int0 must act before select acts when the interrupt type appears on the bus. 56 int0 input/output maskable interrupt request 0. except the interrupt line and interrupt address vector, the function of int0 is the same as int4. timer control unit interface 72 75 tmrin1/pio0 tmrin0/pio11 input/output timer input. these pins can be as clock or control signal input, which depend upon the programmed timer mode. after internally synchronizing low to high transitions on tmrin, the timer controller increments. these pins must be pull-up if not being used. 73 74 tmrout1/pio1 tmrout0/pio10 output/input timer output. depending on timer mode select these pins provide single pulse or continuous waveform. the duty cycle of the waveform can be programmable. these pins are floated during a bus hold or reset. dma unit interface 76 77 drq1/int6/pio13 drq0/int5/pio12 input/output dma request. these pins are asserted high by an external device when the device is ready for dma channel 1 or channel 0 to perform a transfer. these pins are level-triggered and internally synchronized. the drq signals must remain act until finish serviced and are not latched. for int6/int5 function: when the dma function is not being used, int6/int5 can be used as an additional external interrupt request. and they share the corresponding interrupt
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 13 type and register control bits. the int6/5 are edge-triggered only and must be hold until the interrupt is acknowledged. notes: 1.when enable the pio data register, there are 32 mux definition pins can be as a pio pin. for example, the drd1/pio13 ( pin76) can be as a pio13 when enable the pio data register. 2.the pio status during power-on reset : pio1, pio10, pio22, pio23 are input with pull-down, pio4 to pio9 are normal operation and the others are input with pull-up.
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 14 5 . basic application system block x1 x2 rs232 level converter serial port0 timer0-1 int x dma pio ad7-ad0 a19-a0 wr data(8) address ucs rd we oe ce flash rom data(8) address sram data address we oe peripheral cs pcs x R8830LV we oe ce lcs basic application system block (a) rst vcc 100k 1uf serial port1 x1 x2 rs232 level converter serial port0 timer0-1 int x dma pio d7-d0 a19-a0 wr data(8) address ucs rd we oe ce flash rom data(8) address sram data address we oe peripheral cs pcs x R8830LV we oe ce lcs basic application system block (b) rst vcc 100k 1uf dir transciver g latch den dt/r ad7-ad0 ad7-ad0 ale ao15-ao8 a19-a16 serial port1
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 15 6. oscillator characteristics for fundamental -mode crystal: c1 --- 20pf 20 % ; c2 --- 20pf 20% ; rf --- 1 mega-ohm ; c3 , l --- don ? t care for third-overtone mode crystal: c1 --- 20pf 20 % ; c2 --- 20pf 20% ; c3 --- 200pf ; rf --- 1 mega-ohm l --- 3.0uh 20% (40mhz ) , 4.7uh 20% (33mhz) 8.2uh 20% (25mhz ) , 12uh 20% (20mhz) x1 x2 l c2 c1 200pf rf R8830LV c3
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 16 7 . read/write timing diagram clkouta a19:a0 s6 ao15:ao8 ale den dt/r uzi t1 t2 t3 t4 address ucs,lcs s2:s0 tw read cycle pcs x, mcs x address rd ad7:ad0 address data 7 5 7
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 17 clkouta a19:a0 s6 ao15:ao8 ale wr den dt/r uzi t1 t2 t3 t4 address ucs,lcs s2:s0 tw write cycle pcs x, mcs x address ad7:ad0 wb address data 7 6 7
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 18 8. execution unit 8.1 general register the R8830LV has eight 16-bit general registers. and the ax ,bx,cx,dx can be subdivided into two 8-bit register (ah,al,bh, bl ,ch,cl,dh,dl). tthe functions of these registers are described as follows. ax : word divide , word multiply, word i/o operation. ah : byte divide , byte multiply, byte i/o , decimal arithmetic, translate operation. al : byte divide , byte multiply operation. bx : translate operation. cx : loops, string operation cl : variable shift and rotate operation. dx : word divide , word multiply, indirect i/o operation sp : stack operations (pop, popa, popf, push, pusha, pushf) bp : general-purpose register which can be used to determine offset address of operands in memory. si : string operations di : string operations 8.2 segment register R8830LV has four 16-bit segment registers, cs, ds, ss, es. the segment registers contain the base addresses (starting location) of these memory segments, and they are immediately addressable for code (cs), data (ds & es), and stack (ss) memory. accumulator base register count/loop/repeat/shift data stack pointer destination index base pointer source index ax bx cx dx data group index group and pointer general registers ah bh ch dh al bl cl dl sp bp si di 0 7 8 15 high low
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 19 cs (code segment ) : the cs register points to the current code segment, which contains instruction to be fetched. the default location memory space for all instruction is 64k. the initial value of cs register is 0ffffh. ds (data segment ) : the ds register points to the current data segment, which generally contains program variables. the ds register initialize to 0000h. ss (stack segment ) : the ss register points to the current stack segment, which is for all stack operations, such as pushes and pops. the stack segment is used for temporary space. the ss register initialize to 0000h. es (extra segment ) : the es register points to the current extra segment which is typically for data storage, such as large string operations and large data structures. the ds register initialize to 0000h. 8.3 instruction pointer and status flags register ip (instruction pointer ) : the ip is a 16-bit register and it contains the offset of the next instruction to be fetched. software can not to direct access the ip register and this register is updated by the bus interface unit. it can change, be saved or be restored as a result of program execution. the ip register initialize to 0000h and the cs :ip starting execution address is at 0ffff0h. these flags reflect the status after the execution unit is executed. bit 15- 12 : reserved bit 11: of , overflow flag. an arithmetic overflow has occurred , this flag will be set. bit 10 : df , direction flag. if this flag is set, the string instructions are increment address process. if df is cleared, the string instructions are decrement address process. refer the std and cld instructions for how to set and clear the df flag. cs ds ss es 0 7 8 15 code segment data segment stack segment extra segment segment registers processor status flags registers flags 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 res pf res cf af res zf sf tf if df of reserved
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 20 bit 9 : if , interrupt-enable flag. refer the sti and cli instructions for how to set and clear the if flag. set to 1 : the cpu enables the maskable interrupt request. set to 0 : the cpu disables the maskable interrupt request. bit 8: tf , trace flag. set to enable single-step mode for debugging; clear to disable the single-step mode. if an application program sets the tf flag using popf or iret instruction, a debug exception is generated after the instruction (the cpu automatically generates an interrupt after each instruction) that follows the popf or iret instruction. bit 7 : sf, sign flag. if this flag is set, the high-order bit of the result of an operation is 1 , indicating it is negative. bit 6: zf , zero flag. the result of operation is zero, this flag is set. bit 5 : reserved bit 4: af , auxiliary flag. if this flag is set, there has been a carry from the low nibble to the high or a borrow from the high nibble to the low nibble of the al general-purpose register. used in bcd operation. bit 3 : reserved. bit 2: pf , parity flag. the result of low-order 8 bits operation has even parity, this flag is set. bit 1 : reserved bit 0: cf , carry flag. if cf is set, there has been a carry out or a borrow into the high-order bit of the instruction result. 8.4 address generation the execution unit generates a 20-bit physical address to bus interface unit by the address generation. memory is organized in sets of segments. each segment contains a 16 bits value. memory is addressed using a two-component address that consists of a 16-bit segment and 16-bit offset. the physical address generation figure describes how the logical address transfers to the physical address. 1 2 f 9 0 19 0 0 0 1 2 15 0 1 2 f a 2 19 0 to memory 1 2 f 9 0 0 1 2 15 0 15 0 physical address segment base offset logical address shift left 4 bits physical address generation
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 21 9. peripheral control block register the peripheral control block can be mapped into either memory or i/o space which is to program the feh register. and it starts at ff00h in i/o space when reset the microprocessor. the following table is the definition of all the peripheral control block register , and the detail description will arrange on the relation block unit. offset (hex) register name page offset (hex) register name page fe peripheral control block relocation register 22 70 pio mode 0 register 78 f6 reset configuration register 25 66 timer 2 mode / control register 64 f4 processor release level register 22 62 timer 2 maxcount compare a register 65 f2 serial port flow control register 30 60 timer 2 count register 65 f0 system configuration register 23 5e timer 1 mode / control register 62 e6 watchdog timer control register 67 5c timer 1 maxcount compare b register 64 e4 enable rcu register 79 5a timer 1 maxcount compare a register 64 e2 clock prescaler register 79 58 timer 1 count register 64 e0 memory partition register 79 56 timer 0 mode / control register 61 da dma 1 control register 55 54 timer 0 maxcount compare b register 62 d8 dma 1 transfer count register 57 52 timer 0 maxcount compare a register 62 d6 dma 1 destination address high register 57 50 timer 0 count register 61 d4 dma 1 destination address low register 58 44 serial port 0 interrupt control register 40 d2 dma 1 source address high register 58 42 serial port 1 interrupt control register 41 d0 dma 1 source address low register 58 40 int4 control register 42 ca dma 0 control register 54 3e int3 control register 42 c8 dma 0 transfer count register 54 3c int2 control register 43 c6 dma 0 destination address high register 54 3a int1 control register 43 c4 dma 0 destination address low register 55 38 int0 control register 44 c2 dma 0 source address high register 55 36 dma 1/int6 interrupt control register 45 c0 dma 0 source address low register 55 34 dma 0/int5 interrupt control register 45 a8 pcs and mcs auxiliary register 34 32 timer interrupt control register 46 a6 midrange memory chip select register 33 30 interrupt status register 46 a4 peripheral chip select register 35 2e interrupt request register 47 a2 low memory chip select register 32 2c interrupt in-service register 48 a0 upper memory chip select register 31 2a interruptpriority mask register 49 88 serial port 0 baud rate divisor register 74 28 interrupt mask register 50 86 serial port 0 receive register 74 26 interrupt poll status register 51 84 serial port 0 transmit register 73 24 interrupt poll register 51 82 serial port 0 status register 73 22 interrupt end-of-interrupt 51 80 serial port 0 control register 71 20 interrupt vector register 52 7a pio data 1 register 77 18 serial port 1 baud rate divisor 75 78 pio direction 1 register 77 16 serial port 1 receive register 75 76 pio mode 1 register 77 14 serial port 1 transmit register 75 74 pio data 0 register 78 12 serial port 1 status register 74 72 pio direction 0 register 78 10 serial port 1 control register 74
rdc ? risc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 22 the peripheral control block is mapped into either memory or i/o space by programming this register. when the other chip selects ( pcsx or mcsx ) are programmed to zero wait states and ignore the external ready, the pcsx or mcsx can overlap the control block. bit 15 : reserved bit 14 : s/ m , slave/master ? configures the interrupt controller set 0 : master mode, set 1: slaved mode bit 13 : reserved bit 12 : m/ io , memory/io space. at reset, this bit is set to 0 and the pcb map start at ff00h in i/o space. set 1 - the peripheral control block (pcb) is located in memory space. set 0 - the pcb is located in i/o space. bit 11- 0 : r19-r8 , relocation address bits the upper address bits of the pcb base address. the lower eight bits default to 00h. when the pcb is mapped to i/o space, the r19-r16 must be programmed to 0000b. read only register that specifies the processor release version and rdc identify number bit 15- 8 : processor version 01h : version a , 02h : version b, 03h : version c, 04h : version d bit 7- 0 : rdc identify number - d9h peripheral control block relocation register: offset : feh 0 reset value : 20ffh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 res res r19 - r8 m/io s/m processor release level register offset : f4h 0 reset value : f9h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prl 1 1 0 1 1 0 0 1
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 23 10. system clock block bit 15 : psen , enable power-save mode. this bit is cleared by hardware when an external interrupt occurs. this bit does not be changed when software interrupts (int instruction) and exceptions occurs. set 1: enable power-save mode and divides the internal operating clock by the value in f2-f0. bit14 : mcsbit , 0 mcs control bit. set to 0: the 0 mcs operate normally. set to 1: 0 mcs is active over the entire mcsx range bit13-12 : reserved bit 11 : cbf , clkoutb output frequency selection. set 1: clkoutb output frequency is same as crystal input frequency. set 0 : clkoutb output frequency is from the clock divisor, which frequency is same as that of microprocessor internal clock. bit 10 : cbd , clkoutb drive disable set 1: disable the clkoutb. this pin will be three-state. set 0 : enable the clkoutb. bit 9: caf , clkouta output frequency selection. set 1: clkouta output frequency is same as crystal input frequency. set 0 : clkoutb output frequency is from the clock divisor, which frequency is same as that of microprocessor x1 x2 clkin or clkin/2 clock divisior (clk/2-clk/128) mux caf(f0h.9) mux cbf(f0h.11) cad(f0h.8) cbd(f0h.10) f2-f0(f0h.2-f0h.0) psen(f0h.15) clk clkin clkin/2 select s6/clkdiv2 clkouta clkoutb microprocessor internal clock system clock enable/disable divisor select power-save control register offset : f0h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mcsbit psen 0 0 0 0 0 f2 f1 f0 cad caf cbd cbf 0 0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 24 internal clock . bit 8: cad , clkouta drive disable. set 1: disable the clkouta. this pin will be three-state. set 0 : enable the clkouta. bit 7- 3 : reserved bit 2-0: f2- f0, clock divisor select. f2 , f1, f0 ----- divider factor 0, 0, 0 ---- divide by 1 0, 0, 1 ---- divide by 2 0, 1, 0 ---- divide by 4 0, 1, 1 ---- divide by 8 1, 0, 0 ---- divide by 16 1, 0, 1 ---- divide by 32 1, 1, 0 ---- divide by 64 1, 1, 1 ---- divide by 128 11. reset processor initialization is accomplished with activation of the rst pin. to reset the processor, this pin should be held low for at least seven oscillator periods. the reset status figure shows the status of the rst pin and others relation pins. when rst from low go high , the state of input pin (with weakly pull-up or pull-down) will be latched , and each pin will perform the individual function. the ao15-ao8 ,ad7-ad0 will be latched into the register f6h. ucs / 1 once , lcs / 0 once will enter once mode (all of the pins will floating except x1 , x2) when with pull-low resisters. the input clock will divide by 2 when s6/ 2 clkdiv with pull-low resister. theao15-ao8, ad7-ad0 bus will not drive the address phase during ucs , lcs cycle if bhe / aden with pull-low resister
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 25 bit 15- 0 : rc ,reset configuration ad15 ? ad0. the ao15 to ao8, ad7 to ad0 must with weakly pull-up or pull-down resistors to correspond the contents when ao15 to ao8 ,ad7-ad0 be latched into this register during the rst pin from low go high. and the value of the reset configuration register provides the system information when software read this register. this register is read only and the contents remain valid until the next processor reset. reset configuration register offset : f6h 0 reset value : ad15-ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rc clkouta a19-a0 s6 ad7-ad0 ale bhe rd den s2-s0 ffff0 f0 7 4 7 4 min 7t ucs ea reset status (float) (input) (input) (float) (float) (float) (float) (float) dt/r (input) (input) rst ff (input) ao15-ao8
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 26 12. bus interface unit the bus interface unit drives address, data, status and control information to define a bus cycle. the bus a19-a0 are non- multiplex memory or i/o address. the ad15-ad0 are multiplexed address and data bus for memory or i/o accessing. the 2 s - 1 s are encoded to indicate the bus status, which is described in the pin description table in page 5. the basic application system block (page 10) and read/write timing diagram (page 12) describe the basic bus operation. 12.1 memory and i/o interface the memory space consists of 1m bytes (512k 16-bit port) and the i/o space consists of 64k bytes (32k 16-bit port). memory devices exchange information with the cpu during memory read, memory write and instruction fetch bus cycles. i/o read and i/o write bus cycles use a separate i/o address space. only in/out instruction can access i/o address space, and information must be transferred between the peripheral device and the ax register. the first 256 bytes of i/o space can be accessed directly by the i/o instructions. the entire 64k bytes i/o address space can be accessed indirectly, through the dx register. i/o instructions always force address a19-a16 to low level. 12.2 data bus the memory address space data bus is physically implemented by dividing the address space into two banks of up to 512k bytes. each one bank connects to the lower half of the data bus and contains the even-addressed bytes (a0=0). the other memory space fffffh 0 1m bytes i/o space 0ffffh 0 64k bytes memory and i/o space fffff ffffd 5 3 1 ffffe ffffc 4 2 0 512k bytes 512k bytes a19:1 d15:8 bhe d7:0 a0 physical data bus models
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 27 bank connects to the upper half of the data bus and contains odd-addressed bytes (a0=1). a0 and bhe determine whether one bank or both banks participate in the data transfer. 12.3 wait states wait states extend the data phase of the bus cycle. the ardy or srdy input with high level will insert wait states. to avoid wait states, ardy and srdy must be low within a specified setup time prior to phase 2 of t2. to insert wait states, ardy or srdy must drive high within a specified setup time prior to phase 2 of t2 or phase 1 of t3. if the ardy is not used, tie this pin low to yield control to srdy. if the srdy is not used, tie this pin low to yield control to ardy. the srdy/pio6 is multi function pin, and srdy internally pull-down when this pin is programmed for pio function. case 1 case 2 case 3 case 4 t1 tw t3 t2 t2 tw tw t3 t3 tw tw tw t4 t4 t4 t4 clkouta ardy(normally not-ready system) asynchronous ready waveforms ardy(normally ready system) case 1 case 2 case 3 case 4 t1 tw t3 t2 t2 tw tw t3 t3 tw tw tw t4 t4 t4 t4 clkouta synchronous ready waveforms srdy(normally not-ready system) srdy(normally ready system)
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 28 12.4 bus hold when the bus hold requested ( hold pin active high) by the another bus master, the microprocessor will issue a hlda in response to a hold request at the end of t4 or ti. when the microprocessor is in hold status (hlda is high), the ad15- ad0, a19-a0, wr , rd , den , 1 s - 0 s , 6 s , bhe , dt/ r , whb and wlb are floating, and the ucs , lcs , 6 pcs - 5 pcs , 3 mcs - 0 mcs and 3 pcs - 0 pcs will be drive high. after hold is detected as being low, the microprocessor will lower the hlda. clkouta hold hlda a19:a0 den s6 s2:s0 ad15:ad0 rd wr dt/r wlb bus hold enter waveform 2 7 case 1 case 2 ti t3 ti t4 ti ti ti ti floating floating floating floating floating floating floating floating floating
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 29 clkouta hold hlda a19:a0 s6 s2:s0 ad15:ad0 rd wr dt/r wlb address 7 data den 6 bus hold leave waveform case 1 case 2 ti ti ti ti ti t4 t1 t1 floating floating floating floating floating floating floating floating floating ti ti
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 30 12.5 bus width the R8830LV default is 16 bits bus access. and the bus can be programmed as 8-bits or 16-bits access during memory or i/o access is located in the lcs or mcsx or pcsx address space. the ucs code- fetched selection is 16 bits bus width, which can not be changed by programmed the register. bit 15-7 : reserved. bit 6: enrx1 , enable the receiver request of serial port 1. set 1: the 1 cts / 1 enrx pin is configured as 1 enrx set 0: the 1 cts / 1 enrx pin is configured as 1 cts bit 5: rts1 , enable request to send of serial port 1. set 1: the 1 rtr / 1 rts pin is configured as 1 rts set 0: the 1 rtr / 1 rts pin is configured as 1 rtr bit 4: enrx0 , enable the receiver request of serial port 0. set 1: the 0 cts / 0 enrx pin is configured as 0 enrx set 0: the 0 cts / 0 enrx pin is configured as 0 cts bit 3: rts0 , enable request to send of serial port 0. set 1: the 0 rtr / 0 rts pin is configured as 0 rts set 0: the 0 rtr / 0 rts pin is configured as 0 rtr bit 2: lsiz , lcs data bus size selection. this bit can not be changed while executing from lcs space or while the peripheral control block is overlaid with pcs space. set 1: 8 bits data bus access when the memory access located in the lcs memory space. set 0: 16 bits data bus access when the memory access located in the lcs memory space. bit 1: msiz , mcsx , pcsx memory data bus size selection. this bit can not be changed while executing from the associated or while the peripheral control block is overlaid on this address space. set 1: 8 bits data bus access when the memory access locate in the selection memory space. set 0 : 16 bits data bus access when the memory access locate in the selection memory space. bit 0: iosiz , i/o space data bus size selection. this bit determines the width of the data bus for all i/o space accesses. set 1: 8 bits data bus access. set 0 : 16 bits data bus access. auxiliary configuration register offset : f2h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved enrx1 rts1 enrx0 rts0 lsiz msiz iosiz
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 31 13. chip select unit the chip select unit provides 12 programmable chip select pins to access a specific memory or peripheral device. the chip selects are programmed through five peripheral control registers (a0h, a2h, a4h, a6h, a8h). and all of the chip selects can be insert wait states by programmed the peripheral control register. 13.1 ucs the ucs default to active on reset for program code access. the memory active range is upper 512k (80000h ? fffffh), which is programmable. and the default memory active range of ucs is 64k ( f0000h ? fffffh). the ucs active to drive low four clkouta oscillators if no wait state inserts. there are three wait-states insert to ucs active cycle on reset. bit 15 : reserved bit 14- 12 : lb2-lb0 , memory block size selection for ucs chip select pin. the ucs chip select pin active region can be configured by the lb2-lb0. the default memory block size is from f0000h to fffffh. lb2, lb1, lb0 ---- memory block size , start address , end address 1 , 1 , 1 ---- 64k , f0000h , fffffh 1 , 1 , 0 ---- 128k , e0000h , fffffh 1 , 0 , 0 ---- 256k , c0000h , fffffh 0 , 0 , 0 ---- 512k , 80000h , fffffh bit 11- 8 : reserved bit 7 : da , disable address. if the bhe / aden pin is held high on the rising edge of rst , then the da bit is valid to enable/disable the address phase of the ad bus. if the bhe / aden pin is held high on the rising edge of rst , the ad bus always drive the address and data. set 1 : disable the address phase of the ad15 ? ad0 bus cycle when ucs is asserted. set 0 : enable the address phase of the ad15 ? ad0 bus cycle when ucs is asserted. bit 6-3 : reserved bit 2 : r2 , ready mode. this bit is used to configure the ready mode for ucs chip select. set 1: external ready is ignored. set 0: external ready is required. bit 1- 0 : r1-r0 , wait-state value. when r2 is set to 0, it can inserted wait-state into an access to the ucs memory area. upper memory chip select register offset : a0h 0 reset value :f03bh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 lb2 - lb0 0 0 0 0 da 0 1 1 1 r2 r1 r0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 32 (r1 ,r0) = (0,0) -- 0 wait-state ; (r1,r0) = (0,1) -- 1 wait-state (r1 ,r0) = (1,0) -- 2 wait-state ; (r1,r0) = (1,1) -- 3 wait-state 13.2 lcs the lower 512k bytes (00000h-7ffffh) memory region chip selects. the memory active range is programmable, which has no default size on reset. so the a2h register must be programmed first before to access the target memory range. the lcs pin is not active on reset, but any read or write access to the a2h register activates this pin. bit 15 : reserved bit 14- 12 : ub2-ub0, memory block size selection for lcs chip select pin the lcs chip select pin active region can be configured by the ub2-ub0. the lcs pin is not active on reset, but any read or write access to the a2h (lmcs) register activates this pin. ub2, ub1, ub0 ---- memory block size , start address , end address 0 , 0 , 0 ---- 64k , 00000h , 0ffffh 0 , 0 , 1 ---- 128k , 00000h , 1ffffh 0 , 1 , 1 ---- 256k , 00000h , 3ffffh 1 , 1 , 1 ---- 512k , 00000h , 7ffffh bit 11- 8 : reserved bit 7 : da , disable address. if the bhe / aden pin is held high on the rising edge of rst , then the da bit is valid to enable/disable the address phase of the ad bus. if the bhe / aden pin is held low on the rising edge of rst , the ad bus always drive the address and data. set 1 : disable the address phase of the ad15 ? ad0 bus cycle when lcs is asserted. set 0 : enable the address phase of the ad15 ? ad0 bus cycle when lcs is asserted. bit 6 : pse , psram mode enable. this bit is used to enable psram support for the lcs chip select memory space. the refresh control unit registers e0h,e2h,e4h must be configured for auto refresh before psram support is enabled. pse set to 1: psram support is enable pse set to 0: psram support is disable bit 5-3 : reserved bit 2 : r2 , ready mode. this bit is used to configure the ready mode for lcs chip select. set 1: external ready is ignored. low memory chip select register offset : a2h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 ub2 - ub0 1 1 1 1 da pse 1 1 1 r2 r1 r0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 33 set 0: external ready is required. bit 1- 0 : r1-r0 , wait-state value. when r2 is set to 0, it can inserted wait-state into an access to the lcs memory area. (r1 ,r0) = (0,0) -- 0 wait-state ; (r1,r0) = (0,1) -- 1 wait-state (r1 ,r0) = (1,0) -- 2 wait-state ; (r1,r0) = (1,1) -- 3 wait-state 13.3 mcsx the memory block of mcs4 - mcs0 can be located anywhere within the 1m bytes memory space, exclusive of the areas associated with the ucs and lcs chip selects. the maximum mcsx active memory range is 512k bytes. the mcsx chip selects are programmed through two registers a6h and a8h, and these select pins are not active on reset. both a6h and a8h registers must be accessed with a read or write to activate mcs4 - mcs0 . there aren ? t default value on a6h and a8h registers, so the a6h and a8h must be programmed first before mcs4 - mcs0 active. bit 15- 7 : ba19-ba13 , base address. the ba19-ba13 correspond to bits 19-13 of the 1m bytes (20-bits) programmable base address of the mcs chip select block. the bits 12 to 0 of the base address are always 0. the base address can be set to any integer multiple of the size of the memory block size selected in these bits. for example, if the midrange block is 32kbytes, only the bits ba19 to ba15 can be programmed. so the block address could be locate at 20000h or 38000h but not in 22000h. the base address of the mcs chip select can be set to 00000h only if the lcs chip select is not active. and the mcs chip select address range is not allowed to overlap the lcs chip select address range. the mcs chip select address range also is not allowed to overlap the ucs chip select address range. bit 8- 3 : reserved bit 2: r2 , ready mode. this bit is configured to enable/disable the wait states inserted for the mcs chip selects. the r1 ,r0 bits of this register determine the number of wait state to insert. set to 1: external ready is ignored set to 0: external ready is required bit 1- 0 : r1-r0 , wait-state value. the r1 ,r0 determines the number of wait states inserted into a mcs access. (r1 ,r0) : (1,1) ? 3 wait states , (1,0) ? 2 wait states, (0,1) ? 1 wait states , (0,0) ? 0 wait states midranage memory chip select register offset : a6h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ba19 - ba13 1 1 1 1 r2 r1 r0 1
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 34 bit 15 : reserved bit 14-8: m6-m0 , mcs block size. these bits determines the total block size for the mcs3 - mcs0 chip selects. each individual chip select is active for one quarter of the total block size. for example, if the block size is 32k bytes and the base address is located at 20000h. the individual active memory address range of mcs3 to mcs0 is mcs0 ? 20000h to 21fff, mcs1 -22000 to 23fffh, mcs2 - 24000h to 25fffh, mcs3 - 26000h to 27fffh. mcsx total block size is defined by m6-m0, m6- m0 , total block size , mcsx address active range 0000001b , 8k , 2k 0000010b , 16k , 4k 0000100b , 32k , 8k 0001000b , 64k , 16k 0010000b , 128k , 32k 0100000b , 256k , 64k 1000000b , 512k , 128k bit 7 : ex , pin selector. this bit configures the multiplex output which the pcs6 - pcs5 pins as chip selects or a2-a1. set 1 : pcs6 , pcs5 are configured as peripheral chip select pins. set 0: pcs6 is configured as address bit a2, pcs5 is configured as a1. bit 6: ms , memory or i/o space selector. set 1: the pcsx pins are active for memory bus cycle. set 0: the pcsx pins are active for i/o bus cycle. bit 5- 3 : reserved bit 2 : r2 , ready mode. this bit is configured to enable/disable the wait states inserted for the pcs5 ,pcs6 chip selects. the r1 ,r0 bits of this register determine the number of wait state to insert. set to 1: external ready is ignored set to 0: external ready is required bit 1- 0 : r1-r0 , wait-state value. the r1 ,r0 determines the number of wait states inserted into a pcs5 - pcs6 access. (r1 ,r0) : (1,1) ? 3 wait states , (1,0) ? 2 wait states, (0,1) ? 1 wait states , (0,0) ? 0 wait states 13.4 pcsx the peripheral or memory chip selects which are programmed through a4h and a8h register to define these pins. offset : a8h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 m6 - m0 ms 1 1 1 r2 r1 r0 ex 1 pcs and mcs auxiliary register
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 35 the base address memory block can be located anywhere within the 1m bytes memory space, exclusive of the areas associated with the mcs4 , lcs and mcs chip elects. if the chip selects are mapped to i/o space, the access range is 64k bytes. pcs6 ? pcs5 can be configured from 0 wait-state to 3 wait-states. pcs3 ? pcs0 can be configured from 0 wait-state to 15 wait-states. bit 15- 7 : ba19-ba11 , base address. ba19-ba11 correspond to bit 19-11 of the 1m bytes (20-bits) programmable base address of the pcs chip select block. when the pcs chip selects are mapped to i/o space, ba19-ba16 must be wrote to 0000b because the i/o address bus in only 64k bytes (16-bits) wide. pcsx address range: pcs0 : base address - base address+255 pcs1 : base address+256 - base address+511 pcs2 : base address+512 - base address+767 pcs3 : base address+768 - base address+1023 pcs4 : base address+1280 - base address+1535 pcs5 : base address+1536 - base address+1791 bit 6-4 : reserved bit 3: r3 ; bit 1-0: r1 ,r0 ,wait-state value. the r3 ,r1,r0 determines the number of wait-states inserted into a pcs3 - pcs0 access. r3 , r1, r0 -- wait states 0, 0, 0 -- 0 0, 0, 1 -- 1 0, 1, 0 -- 2 0, 1, 1 -- 3 1, 0, 0 -- 5 1, 0, 1 -- 7 1, 1, 0 -- 9 1, 1, 1 -- 15 bit 2 : r2 , ready mode. this bit is configured to enable/disable the wait states inserted for the pcs3 - pcs0 chip selects. the r3 ,r1,r0 bits determine the number of wait state to insert. set to 1: external ready is ignored peripheral chip select register offset : a4h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ba19 - ba11 1 1 1 r3 r2 r1 r0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 36 set to 0: external ready is required
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 37 14. interrupt controller unit there are 16 interrupt requests source connect to the controller: 7 maskable interrupt pins ( int0 ? int6); 2 non- maskable interrupts (nmi pin , wdt) ; 7 internal unit request source ( timer 0, 1,2 ;dma 0,1 ; asynchronous serial port 0, 1). 14.1 master mode and slave mode the interrupt controller can be programmed as a master or slave mode. ( program feh , bit 14). the master mode has two connections : fully nested mode connection or cascade mode connection. R8830LV interrupt source int0 int1 int2 int3 int4 interrupt source interrupt source interrupt source interrupt source fully nested mode connections int5 int6 interrupt source interrupt source interrupt control logic 0 0 0 1 1 1 master/slave mode select (feh.14) timer0/1/2 interrupt req. timer0 req. int0 timer1 req. timer2 req. dma0 interrupt req. dma1 interrupt req. int2 int3 int4 asynchronous serial port 0 execation unit interrupt type interrupt req. in-service register eoi register acknowledge acknowledge to dma, timer,serial port unit internal address/data bus 16 bit 16 bit interrupt control unit block diagram asynchronous serial port 1 int5 int6 nmi nmi watchdog timer
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 38 14.2 interrupt vector, type and priority the following table shows the interrupt vector addresses, type and the priority. the maskable interrupt priority can be changed by programmed the priority register. the vector addresses for each interrupt are fixed. interrupt source interrupt type vector address eoi type priority note divide error exception 00h 00h 1 trace interrupt 01h 04h 1-1 * nmi 02h 08h 1-2 * breakpoint interrupt 03h 0ch 1 slave mode connection int0 inta0 irq 8259 R8830LV cascade address dccode select cascade mode connection int0 inta0 int1 inta1 8259 ir7 8259 ir7 cas3-cas0 cas3-cas0 R8830LV 8259 cas3-cas0 8259 cas3-cas0 int inta int inta interrupt sources interrupt sources interrupt sources interrupt sources int4 int5 int6
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 39 into detected over flow exception 04h 10h 1 array bounds exception 05h 14h 1 undefined opcode exception 06h 18h 1 esc opcode exception 07h 1ch 1 timer 0 08h 20h 08 2-1 */** reserved 09h dma 0/int5 0ah 28h 0a 3 ** dma 1/int6 0bh 2ch 0b 4 ** int0 0ch 30h 0c 5 int1 0dh 34h 0d 6 int2 0eh 38h 0e 7 int3 0fh 3ch 0f 8 int4 10h 40h 10 9 asynchronous serial port 1 11h 44h 11 9 timer 1 12h 48h 08 2-2 */** timer 2 13h 4ch 08 2-3 */** asynchronous serial port 0 14h 50h 14 9 reserved 15h-1fh note * : when the interrupt occurs in the same time, the priority is (1-1 > 1-2) ; (2-1> 2-2 > 2-3) note **: the interrupt types of these sources are programmable in slave mode. 14.3 interrupt request when an interrupt is request, the internal interrupt controller verifies the interrupt is enable (the if flag is enable, no msk bit set ) and that there are no higher priority interrupt requests being serviced or pending. if the interrupt is granted , the interrupt controller uses the interrupt type to access a vector from the interrupt vector table. if the external int is active (level-trigger) to request the interrupt controller service, and the int pins must hold till the microcontroller enter the interrupt service routine. there is no interrupt-acknowledge output when running in fully nested mode, so it should use pio pin to simulate the interrupt-acknowledge pin if necessary. 14.4 interrupt acknowledge the processor requires the interrupt type as an index into the interrupt table. the internal interrupt can provide the interrupt type or an external controller can provide the interrupt type. the internal interrupt controller provides the interrupt type to processor without external bus cycles generation. when an external interrupt controller is supplying the interrupt type, the processor generates two acknowledge bus cycles, and the interrupt type is written to the ad7-ad0 lines by the external interrupt controller.
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 40 14.5 programming the registers software is programmed through the registers ( master mode: 44h, 42h, 40h, 3eh, 3ch, 3ah, 38h, 36h, 34h, 32h, 30h, 2eh, 2ch, 2ah, 28h, 26h, 24h, 22h; slave mode: 3ah, 38h, 36h, 34h, 32h, 30h, 2eh, 2ch, 2ah, 28h,22h, 20h ) to define the interrupt controller operation. (master mode) bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the asynchronous serial port 0. set 0: enable the serial port 0 interrupt. bit 2- 0 : pr2-pr0 , priority. these bits determine the priority of the serial port relative to the other interrupt signals. 7 0 7 0 clkouta address[19:0] s6 ad15:ad0 ale bhe den s2:s0 interrupt acknowledge cycle (casecade or slave mode) intr ack intr ack address dt/r t1 t2 t3 t4 t1 t2 t3 t4 interrupt type inta0,inta1 serial port 0 interrupt control register offset : 44h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved 1 msk pr2 pr1 pr0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 41 the priority selection: pr2 , pr1 , pr0 -- priority 0 , 0 , 0 -- 0 ( high) 0 , 0 , 1 -- 1 0 , 1 , 0 -- 2 0 , 1 , 1 -- 3 1 , 0 , 0 -- 4 1 , 0 , 1 -- 5 1 , 1 , 0 -- 6 1 , 1 , 1 -- 7 ( low ) (master mode) bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the asynchronous serial port 1. set 0: enable the serial port 1 interrupt. bit 2- 0 : pr2-pr0 , priority. these bits determine the priority of the serial port relative to the other interrupt signals. the priority selection: pr2 , pr1 , pr0 -- priority 0 , 0 , 0 -- 0 ( high) 0 , 0 , 1 -- 1 0 , 1 , 0 -- 2 0 , 1 , 1 -- 3 1 , 0 , 0 -- 4 1 , 0 , 1 -- 5 1 , 1 , 0 -- 6 1 , 1 , 1 -- 7 ( low ) serial port 1 interrupt control register offset : 42h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved 1 msk pr2 pr1 pr0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 42 (master mode) bit 15- 8, bit 6- 5 : reserved bit 7: etm , edge trigger enable. when this bit set to 1 and bit 4 set to 0, interrupt is triggered by low go high edge. bit 4: ltm , level-triggered mode. set 1: interrupt is triggered by high active level set 0 : interrupt is triggered by low go high edge. bit 3 : msk , mask. set 1: mask the interrupt source of the int4 set 0: enable the int4 interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of 44h (master mode) bit 15- 8, bit 6- 5 : reserved bit 7: etm , edge trigger enable. when this bit set to 1 and bit 4 set to 0, interrupt is triggered by low go high edge. bit 4: ltm , level-triggered mode. set 1: interrupt is triggered by high active level set 0 : interrupt is triggered by low go high edge. bit 3 : msk , mask. set 1: mask the interrupt source of the int3 set 0: enable the int3 interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of 44h int4 control register offset : 40h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm etm int3 control register offset : 3eh 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm etm
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 43 (master mode) bit 15- 8, bit 6- 5 : reserved bit 7: etm , edge trigger enable. when this bit set to 1 and bit 4 set to 0, interrupt is triggered by low go high edge. bit 4: ltm , level-triggered mode. set 1: interrupt is triggered by high active level set 0 : interrupt is triggered by low go high edge. bit 3 : msk , mask. set 1: mask the interrupt source of the int2 set 0: enable the int2 interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (master mode) bit 15- 8 : reserved bit 7: etm , edge trigger enable. when this bit set to 1 and bit 4 set to 0, interrupt is triggered by low go high edge. bit 6: sfnm, special fully nested mode. set 1: enable the special fully nested mode of int1 bit 5: c, cascade mode. set this bit to 1 to enable the cascade mode for int1 or int0. bit 4: ltm , level-triggered mode. set 1: interrupt is triggered by high active level set 0 : interrupt is triggered by low go high edge. bit 3 : msk , mask. set 1: mask the interrupt source of the int1 set 0: enable the int1 interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h int2 control register offset : 3ch 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm etm int1 control register offset : 3ah 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm c sfnm etm
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 44 (slave mode ) , this register is for timer 2 interrupt control, reset value is 0000h bit 15- 4 : reserved bit 3 : msk , mask. set 1: mask the interrupt source of the timer 2 set 0: enable the timer 2 interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (master mode) bit 15- 8 : reserved bit 7: etm , edge trigger enable. when this bit set to 1 and bit 4 set to 0, interrupt is triggered by low go high edge. bit 6: sfnm, special fully nested mode. set 1: enable the special fully nested mode of int0. bit 5: c, cascade mode. set this bit to 1 to enable the cascade mode for int1 or int0. bit 4: ltm , level-triggered mode. set 1: interrupt is triggered by high active level set 0 : interrupt is triggered by low go high edge. bit 3 : msk , mask. set 1: mask the interrupt source of the int0 set 0: enable the int0 interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (slave mode) ,for timer 1 interrupt control register, reset value is 0000h bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the timer 1 set 0: enable the timer 1 interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h int0 control register offset : 38h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved msk pr2 pr1 pr0 ltm c sfnm etm
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 45 (master mode) bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 1 controller set 0: enable the dma 1 controller interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (slave mode), reset value is 0000h bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 1 controller set 0: enable the dma 1 controller interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (master mode) bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 0 controller set 0: enable the dma 0 controller interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (slave mode), reset value is 0000h dma 1/int6 interrupt control register offset : 36h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 dma 0/int5 interrupt control register offset : 34h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 46 bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the dma 0 controller set 0: enable the dma 1 controller interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (master mode) bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the timer controller set 0: enable the timer controller interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (slave mode), reset value is 0000h bit 15- 4 : reserved bit 3: msk , mask. set 1: mask the interrupt source of the timer 0 controller set 0: enable the timer 0 controller interrupt. bit 2-0: pr , interrupt priority these bits setting for priority selection is same as bit 2-0 of the register 44h (master mode), reset value undefine bit 15 : dhlt , dma halt. timer interrupt control register offset : 32h 0 reset value : 000fh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msk pr2 pr1 pr0 0 0 0 0 0 0 0 0 0 0 0 0 interrupt status register offset : 30h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved tmr2 tmr1 tmr0 dhlt
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 47 set 1: halts any dma activity. when non- maskable interrupts occur. set 0: when an iret instruction is executed. bit 14- 3 : reserved. bit 2- 0 : tmr2-tmr0 , set 1: indicates the corresponding timer has an interrupt request pending. (slave mode), reset value is 0000h bit 15 : dhlt , dma halt. set 1: halts any dma activity. when non- maskable interrupts occur. set 0: when an iret instruction is executed. bit 14- 3 : reserved. bit 2- 0 : tmr2-tmr0 , set 1: indicates the corresponding timer has an interrupt request pending. (master mode) the interrupt request register is a read-only register. for internal interrupts (sp0, sp1, d1/i6, d0/i5, and tmr), the corresponding bit is set to 1 when the device requests an interrupt. the bit is reset during the internally generated interrupt acknowledge. for int4-int0 external interrupts, the corresponding bit (i4-i0) reflects the current value of the external signal. bit 15- 11 : reserved. bit 10 : sp0 , serial port 0 interrupt request. indicates the interrupt state of the serial port 0. bit 9 : sp1 , serial port 1 interrupt request. indicates the interrupt state of the serial port 1. bit 8- 4 : i4-i0 , interrupt requests. set 1: the corresponding int pin has an interrupt pending. bit 3- 2 : d1/i6-d0/i5 , dma channel or int interrupt request. set 1: the corresponding dma channel or int has an interrupt pending. bit 1: reserved. bit 0 : tmr , timer interrupt request. set 1: the timer control unit has an interrupt pending. interrupt request register offset : 2eh 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr d1/i6 i0 i1 i2 i3 i4 sp1 sp0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 48 (slave mode) the interrupt request register is a read-only register. for internal interrupts (d1/i6, d0/i5, tmr2, tmr1, and tmr0), the corresponding bit is set to 1 when the device requests an interrupt. the bit is reset during the internally generated interrupt acknowledge. bit 15- 6 : reserved. bit 5- 4 : tmr2/tmr1 , timer2/timer1 interrupt request. set 1: indicates the state of any interrupt requests form the associated timer. bit 3- 2 : d1/i6-d0/i5 , dma channel or int interrupt request. set 1: indicates the corresponding dma channel or int has an interrupt pending. bit 1 : reserved. bit 0 : tmr0 , timer 0 interrupt request. set 1: indicates the state of an interrupt request from timer 0. (master mode) the bits in the inserv register are set by the interrupt controller when the interrupt is taken. each bit in the register is cleared by writing the corresponding interrupt type to the eoi register. bit 15- 11 : reserved. bit 10 : sp0 , serial port 0 interrupt in-service. set 1: the serial port 0 interrupt is currently being serviced. bit 9 : sp1 , serial port 1 interrupt in-service. set 1: the serial port 1 interrupt is currently being serviced. bit 8- 4 : i4-i0 , interrupt in-service. set 1: the corresponding int interrupt is currently being serviced. bit 3- 2 : d1/i6-d0/i5 , dma channel or int interrupt in-service. s et 1: the corresponding dma channel or int interrupt is currently being serviced. bit 1 : reserved. interrupt request register offset : 2eh 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr0 d1/i6 tmr1 tmr2 in - service register offset : 2ch 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr d1/i6 i0 i1 i2 i3 i4 sp1 sp0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 49 bit 0 : tmr , timer interrupt in-service. set 1: the timer interrupt is currently being serviced. (slave mode) the bits in the in-service register are set by the interrupt controller when the interrupt is taken. the in- service bits are cleared by writing to the eoi register. bit 15- 6 : reserved. bit 5- 4 : tmr2-tmr1 , timer2/timer1 interrupt in-service. set 1: the corresponding timer interrupt is currently being serviced. bit 3- 2 : d1/i6-d0/i5 , dma channel or int interrupt in-service. set 1: the corresponding dma channel or int interrupt is currently being serviced. bit 1 : reserved. bit 0 : tmr0 , timer 0 interrupt in-service. set 1: the timer 0 interrupt is currently being serviced. (master mode) determining the minimum priority level at which maskable interrupts can generate an interrupt. bit 15- 3 : reserved. bit 2- 0 : prm2-prm0 , priority field mask. determining the minimum priority that is required in order for a maskable interrupt source to generate an interrupt. priority pr2-pr0 (high) 0 000 1 001 2 010 3 011 4 100 5 101 6 110 priority mask register offset : 2ah 0 reset value : 0007h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 prm2 prm1 prm0 0 0 0 0 0 0 0 0 0 0 0 0 0 in - service register offset : 2ch 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0 res tmr0 d1 tmr1 tmr2
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 50 (low) 7 111 (slave mode) determining the minimum priority level at which maskable interrupts can generate an interrupt. bit 15- 3 : reserved. bit 2- 0 : prm2-prm0 , priority field mask. determining the minimum priority that is required in order for a maskable interrupt source to generate an interrupt. priority pr2-pr0 (high) 0 000 1 001 2 010 3 011 4 100 5 101 6 110 (low) 7 111 (master mode) bit 15- 11 : reserved. bit 10 : sp0 , serial port 0 interrupt mask. the state of the mask bit of the asynchronous serial port 0 interrupt. bit 9 : sp1 , serial port 1 interrupt mask. the state of the mask bit of the asynchronous serial port 1 interrupt. bit 8- 4 : i4-i0 , interrupt masks. indicates the state of the mask bit of the corresponding interrupt. bit 3- 2 : d1/i6-d0/i5 , dma channel or int interrupt masks. indicates the state of the mask bit of the corresponding dma channel or int interrupt. bit 1: reserved. bit 0 : tmr , timer interrupt mask. the state of the mask bit of the timer control unit . (slave mode) bit 15- 6 : reserved. interrupt mask register offset : 28h 0 reset value : 07fdh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d0/i5 res tmr d1/i6 i0 i1 i2 i3 i4 sp1 sp0 reserved interrupt request register offset : 28h 0 reset value : 003dh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved d0/i5 res tmr0 d1/i6 tmr1 tmr2
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 51 bit 5- 4 : tmr2-tmr1 , timer 2/timer1 interrupt mask. the state of the mask bit of the timer interrupt control register. set 1: timer2 or time1 has its interrupt requests masked bit 3- 2 : d1/i6-d0/i5 , dma channel or int interrupt mask. indicating the state of the mask bits of the corresponding dma or int6/int5 control register. bit 1 : reserved. bit 0 : tmr0 , timer 0 interrupt mask. the state of the mask bit of the timer interrupt control register (master mode) the poll status (pollst) register mirrors the current state of the poll register. the pollst register can be read without affecting the current interrupt request. bit 15 : ireq , interrupt request. set 1: if an interrupt is pending. the s4-s0 field contains valid data. bit 14- 5 : reserved. bit 4- 0 : s4-s0 , poll status. indicates the interrupt type of the highest priority pending interrupt. (master mode) when the poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the poll register. bit 15 : ireq , interrupt request. set 1: if an interrupt is pending. the s4-s0 field contains valid data. bit 14- 5 : reserved. bit 4- 0 : s4-s0 , poll status. indicates the interrupt type of the highest priority pending interrupt. poll status register offset : 26h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s4 - s0 reserved ireq poll register offset : 24h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s4 - s0 reserved ireq end - of - interrupt offset : 22h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s4 - s0 nspec
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 52 (master mode) bit 15 : nspec , non-specific eoi. set 1: indicates non-specific eoi. set 0: indicates the specific eoi interrupt type in s4-s0. bit 14- 5 : reserved. bit 4-0: s4-s0 , source eoi type. specifies the eoi type of the interrupt that is currently being processed. (slave mode) bit 15- 3 : reserved. bit 2- 0 : l2-l0, interrupt type. encoded value indicating the priority of the is(interrupt service) bit to reset. writes to these bits cause an eoi to be issued for the interrupt type in slave mode. ( slave mode) bit 15- 8 : reserved bit 7- 3 : t4-t0, interrupt type. the following interrupt type of slave mode can be programmed. timer 2 interrupt controller : (t4,t3,t2,t1,t0, 1, 0, 1)b timer 1 interrupt controller : (t4,t3,t2,t1,t0, 1, 0, 0)b dma 1 interrupt controller : (t4,t3,t2,t1,t0, 0, 1, 1)b dma 0 interrupt controller : (t4,t3,t2,t1,t0, 0, 1, 0)b timer 0 interrupt controller : (t4,t3,t2,t1,t0, 0, 0, 0)b bit 2- 0 : reserved interrupt vector register offset : 20h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 t4 - t0 0 0 0 0 0 0 0 0 0 0 0 end - of - interrupt offset : 22h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 l2 l1 l0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 53 15 dma unit the dma controller provides the data transfer between the memory and peripherals without the intervention of the cpu. there are two dma channels in the dma unit. each channel can accept dma request from one of three sources: external pin (drq0 for channel 0 or drq1 for channel 1) or serial port (port 0 or port 1) or timer 2 overflow. the data transfer from source to destination can be memory to memory ,or memory to i/o, or i/o to i/o, or i/o to memory. either bytes or words can be transferred to or from even or odd addresses and two bus cycles are necessary (read from source and write to destination) for each data transfer. 15.1 dma operation every dma transfer consists of two bus cycles (figure of typical dma transfer) and the two bus cycles can not be separated by a bus hold request, a refresh request or another dma request. the registers ( cah, c8h, c6h, c4h, c2h, c0h, dah, d8h, d6h, d4h, d2h, d0h) are used to configure and operate the two dma channels. dma control logic adder control logic 20-bit adder/subtractor c8h-transfer counter channel 0 c6h,c4h-destination address channel 0 c2h,c0h-source address channel 0 d8h-transfer counter channel 1 d6h,d4h-destination address channel 1 d2h,d0h-source address channel 1 request arbitration logic int interrupt request cah.8-channel 0 cah.8-channel 1 channel control register1,dah channel control register0,cah internal address/data bus timer 2 request drq0 drq1 tdrq cah.4-channel 0 dah.4-channel 1 20 bit 20 bit 16 bit dma unit block serial port0 serial port1
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 54 the definition of bits 15-0 for dma0 are same as the bits 15-0 of register dah for dma1. bit 15-0 : tc15-tc0, dma 0 transfer count. the value of this register is decremented by 1 after each transfer. bit 15-4 : reserved clkouta ale a19-a0 ad15-ad0 rd wr t1 t2 t3 t4 t1 t2 t3 t4 address address address data address data typical dma trarsfer dma transfer count register offset : c8h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc15 - tc0 dma destination address high register offset : c6h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved dda19 - dda16 dma control registers offset : cah (dma0) 0 reset value : fff9h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc sinc sdec dinc ddec st chg res tdrq p syn0 syn1 int b/w sm/io dm/io
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 55 bit 3-0: dda19-dda16 , high dma 0 destination address. these bits are map to a19- a16 during a dma transfer when the destination address is in memory space or i/o space. if the destination address is in i/o space (64kbytes), these bits must be programmed to 0000b. bit 15-0: dda15-dda0 , low dma 0 destination address. these bits are mapped to a15- a0 during a dma transfer. the value of (dda19-dda0 )b will increment or decrement by 2 after each dma transfer. bit 15-4 : reserved bit 3-0: dsa19-dsa16 , high dma 0 source address. these bits are mapped to a19- a16 during a dma transfer when the source address is in memory space or i/o space. if the source address is in i/o space (64kbytes), these bits must be programmed to 0000b. bit 15-0: dsa15-dsa0 , low dma 0 source address. these bits are mapped to a15- a0 during a dma transfer. the value of (dsa19-dsa0 )b will increment or decrement by 2 after each dma transfer. dma destination address low register offset : c4h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dda15 - dda0 dma source address high register offset : c2h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa19 - dsa16 dma source address low register offset : c0h (dma0) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa15 - dsa0 dma control registers offset : dah (dma1) 0 reset value : fff9h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc sinc sdec dinc ddec st chg res tdrq p syn0 syn1 int b/w sm/io dm/io
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 56 bit 15: dm / io , destination address space select. set 1: the destination address is in memory space. set 0: the destination address is in i/o space. bit 14: ddec , destination decrement. set 1: the destination address is automatically decrement after each transfer. the b /w (bit 0) bit determines the decrement value which is by 1 or 2 when both ddec and dinc bits are set to 1, the address remains constant set 0 : disable the decrement function. bit 13: dinc , destination increment. set 1: the destination address is automatically increment after each transfer. the b /w (bit 0) bit determines the increment value which is by 1 or 2 set 0 : disable the decrement function. bit 12: sm/ io , source address space select. set 1: the source address is in memory space. set 0: the source address is in i/o space bit 11: sdec , source decrement. set 1: the source address is automatically decrement after each transfer. the b /w (bit 0) bit determines the decrement value which is by 1 or 2 when both sdec and sinc bits are set to 1, the address remains constant set 0 : disable the decrement function. bit 10: sinc , source increment. set 1: the source address is automatically increment after each transfer. the b /w (bit 0) bit determines the increment value which is by 1 or 2 set 0 : disable the decrement function bit 9 : tc , terminal count. set 1: the synchronized dma transfer is terminated when the dma transfer count register reaches 0. set 0: the synchronized dma transfer is terminated when the dma transfer count register reaches 0. unsynchronized dma transfer is always terminated when the dma transfer count register reaches 0, regardless the setting of this bit. bit 8 : int , interrupt. set 1: dma unit generates an interrupt request when complete the transfer count . the tc bit must set to 1 to generate an interrupt. bit 7-6: syn1-syn0 , synchronization type selection. syn1 , syn0 -- synchronization type 0 , 0 -- unsynchronized 0 , 1 -- source synchronized
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 57 1 , 0 -- destination synchronized 1 , 1 -- reserved bit 5: p , priority. set 1: it selects high priority for this channel when both dma 0 and dma 1 are transfer in same time. bit 4: tdrq , timer enable/disable request set 1: enable the dma requests from timer 2. set 0: disable the dma requests from timer 2. bit 3: reserved bit 2: chg , changed start bit. this bit must set to 1 when will modify the st bit. bit 1: st , start/stop dma channel. set 1: start the dma channel set 0: stop the dma channel bit 0 : b /w , byte/word select. set 1: the address is incremented or decremented by 2 after each transfer. set 0 :the address is incremented or decremented by 1 after each transfer. bit 15-0 : tc15-tc0, dma 1 transfer count. the value of this register is decremented by 1 after each transfer. bit 15-4 : reserved bit 3-0: dda19-dda16 , high dma 1 destination address. these bits are map to a19- a16 during a dma transfer when the destination address is in memory space or i/o space. if the destination address is in i/o space (64kbytes), these bits must be programmed to 0000b. dma transfer count register offset : d8h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tc15 - tc0 dma destination address high register offset : d6h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved dda19 - dda16
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 58 bit 15-0: dda15-dda0 , low dma 1 destination address. these bits are mapped to a15- a0 during a dma transfer. the value of (dda19-dda0 )b will increment or decrement by 2 after each dma transfer. bit 15-4 : reserved bit 3-0: dsa19-dsa16 , high dma 1 source address. these bits are mapped to a19- a16 during a dma transfer when the source address is in memory space or i/o space. if the source address is in i/o space (64kbytes), these bits must be programmed to 0000b. bit 15-0: dsa15-dsa0 , low dma 1 source address. these bits are map to a15- a0 during a dma transfer. the value of (dsa19-dsa0 )b will increment or decrement by 2 after each dma transfer. 15.2 external requests external dma requests are asserted on the drq pins. the drq pins are sampled on the falling edge of clkouta. it takes a minimum of four clocks before the dma cycle is initiated by the bus interface. the dma request is cleared four clocks before the end of the dma cycle. and no dma acknowledge is provided, since the chip-selects ( mcsx, pcsx) can be programmed to be active for a given block of memory or i/o space, and the dma source and destination address registers can be programmed to point to the same given block. dma transfer can be either source or destination synchronized, and it can also be unsynchronized. the source-synchronized transfer figure shows the typical source-synchronized transfer which provides the source device at least three clock cycles from the time it is acknowledged to deassert its drq line. dma destination address low register offset : d4h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dda15 - dda0 dma source address low register offset : d0h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa15 - dsa0 dma source address high register offset : d2h (dma1) 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dsa19 - dsa16 reserved
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 59 the destination-synchronized transfer figure shows the typical destination-synchronized transfer which differs from a source- synchronized transfer in that two idle states are added to the end of the deposit cycle. the two idle states extend the dma cycle to allow the destination device to deassert its drq pin four clocks before the end of the cycle. if the two idle states were not inserted, the destination device would not have time to deassert its drq signal. clkouta drq(case1) drq(case2) fetch cycle fetch cycle source-synchronized transfers t1 t2 t3 t4 t1 t2 t3 t4 notes: case1 : current source synchronized transfer will not be immediately followed by another dma transfer. case2 : current source synchronized transfer will be immediately followed by antoher dma transfer. clkouta drq(case1) drq(case2) fetch cycle fetch cycle destination-synchronized transfers t1 t2 t3 t4 t1 t2 t3 t4 ti ti netes: case1 : current destination synchronized transfer will not be immediately followed by another dma transfer. case2 : current destination synchronized transfer will be immediately followed by another dma transfer.
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 60 15.3 serial port/dma transfer the serial port data can be dma transfer to or from memory ( or io) space. and the b /w bit of dma control register must be set 1 for byte transfer. the map address of transmit data register is written to the dma destination address register and the memory (or i/o) address is written to the dma source address register, when transmit data. the map address of receive data register is written to the dma source address register and the memory (or i/o) address is written to the dma destination address register, when receive data. the software is programmed through the serial port control register to perform the serial port/ dma transfer. when a dma channel is in use by a serial port, the corresponding external dma request signal is deactivated. for dma to the serial port, the dma channel should be configured as destination synchronized. for dma from the serial port, the dma channel should be configured as source synchronized.
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 61 16. timer control unit there are three 16-bit programmable timers in the R8830LV. the timer operation is independent of the cpu. the three timers can be programmed as a timer element or as a counter element. timers 0 and 1 are each connect to two external pins (tmrin0, tmrout0, tmrin1, tmrout1) which can be used to count or time external events, or they can be used to generate a variable-duty-cycle waveforms. timer 2 is not connected any external pins. it can be used as a prescale to timer 0 and timer 1 or as a dma request source. these bits definition for timer 0 are same as the bits of register 5eh for timer 1. offset : 50h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 count register tc15 - tc0 counter element & control logic microprocessor clock 50h,timer 0 count register 58h,timer 1 compare register 52h,54h,timer0 maxcount compare register 5ah,5ch,timer 1 maxcount compare register 62h,timer 2 count register 60h,timer 2 count register interrupt request 5eh,timer 1 control register 56h,timer 0 control register internal address/data bus tmrout1 tmrout2 16 bit 16 bit timer / counter unit block 16 bit dma request 66h,timer 2 control register tmrin1 tmrin0 (timer2) (timer0,1,2) offset : 56h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 mode / control register cont alt ext p rtg mc 0 0 0 0 0 riu int en 0 inh
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 62 bit 15 ? 0: tc15-tc0 , timer 0 count value. this register contains the current count of timer 0. the count is incremented by one every four internal processor clocks or by prescaled the timer 2, or by one every four external clock which is configured the external clock select bit to refer the tmrin1 signal. bit 15- 0 : tc15 ? tc0 , timer 0 compare a value. bit 15- 0 : tc15 ? tc0 , timer 0 compare b value. bit 15: en , enable bit. set 1: the timer 1 is enable. set 0: the timer 1 is inhibited from counting. the inh bit must be set 1 during writing the en bit, and the inh bit and en bit must be in the same write. bit 14: inh , inhibit bit. this bit is allows selective updating the en bit. the inh bit must be set 1 during writing the en bit, and both the inh bit and en bit must be in the same write. this bit is not stored and is always read as 0. bit 13: int , interrupt bit. set 1: a interrupt request is generated when the count register equals a maximum count. if the timer is configured in dual max-count mode, an interrupt is generated each time the count reaches max-count a or max-count b set 0: timer 1 will not issue interrupt request. bit 12: riu , register in use bit. set 1: the maxcount compare b register of timer 1 is being used offset : 52h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 maxcount compare a register tc15 - tc0 offset : 54h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 0 maxcount compare b register tc15 - tc0 offset : 5eh 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 mode / control register cont alt ext p rtg mc 0 0 0 0 0 riu int en 0 inh
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 63 set 0: the maxcount compare a register of timer 1 is being used bit 11- 6 : reserved. bit 5: mc , maximum count bit. when the timer reaches its maximum count, the mc bit will set to 1 by h/w. in dual maxcount mode, this bit is set each time either maxcount compare a or maxcount compare b register is reached. this bit is set regardless of the en bit (66h.15). bit 4: rtg , re-trigger bit. this bit define the control function by the input signal of tmrin1 pin. when ext=1 (5eh.2), this bit is ignored. set 1: timer1 count register (58h) counts internal events; reset the counting on every tmrin1 input signal from low go high (rising edge trigger). set 0: low input holds the timer 1 count register (58h) value; high input enables the counting which counts internal events. the definition of setting the ( ext , rtg ) ( 0 , 0 ) ? timer1 counts the internal events. if the tmrin1 pin remains high. ( 0 , 1 ) -- timer1 counts the internal events; count register reset on every rising transition on the tmrin1 pin ( 1 , x ) -- tmrin1 pin input acts as clock source and timer1 count register increase one every four external clock. bit 3: p , prescaler bit. this bit and ext(5eh.2) define the timer 1 clock source. the definition of setting the ( ext , p ) ( 0 , 0 ) ? timer1 count register increase one every four internal processor clock. ( 0 , 1 ) ? timer1 count register increase one which prescal by timer 2. ( 1 , x ) -- tmrin1 pin input acts as clock source and timer1 count register increase one every four external clock. bit 2: ext , external clock bit. set 1: timer 1 clock source from external set 0: timer 1 clock source from internal bit 1 : alt , alternate compare bit. this bit controls whether the timer runs in single or dual maximum count mode. set 1: specify dual maximum count mode. in this mode the timer counts to maxcount compare a, then resets the count register to 0. then the timer counts to maxcount compare b, then resets the count register to 0 again, and starts over with maxcount compare a. set 0: specify single maximum count mode. in this mode the timer will count to the valve contained in maxcount compare a and reset to 0, and then the timer counts to maxcount compare a again. maxcount compare b is not used in this mode. bit 0: cont , continuous mode bit. set 1: the timer to run continuously. set 0: the timer will halt after each counting to the maximum count and the en bit will be cleared.
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 64 bit 15 ? 0: tc15-tc0 , timer 1 count value. this register contains the current count of timer 1. the count is incremented by one every four internal processor clocks or by prescaled the timer 2, or by one every four external clock which is configured the external clock select bit to refer the tmrin1 signal. 3bit 15- 0 : tc15 ? tc0 , timer 1 compare a value. bit 15- 0 : tc15 ? tc0 , timer 1 compare b value. bit 15: en , enable bit. set 1: the timer 2 is enable. set 0: the timer 2 is inhibited from counting. the inh bit must be set 1 during writing the en bit, and the inh bit and en bit must be in the same write. bit 14: inh , inhibit bit. this bit is allows selective updating the en bit. the inh bit must be set 1 during writing the en bit, and both the inh bit and en bit must be in the same write. this bit is not stored and is always read as 0. bit 13: int , interrupt bit. offset : 58h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 count register tc15 - tc0 offset : 5ah 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 maxcount compare a register tc15 - tc0 offset : 66h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 2 mode / control register cont 0 0 0 0 mc 0 0 0 0 0 0 int en 0 inh offset : 5ch 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 1 maxcount compare b register tc15 - tc0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 65 set 1: a interrupt request is generated when the count register equals a maximum count. set 0: timer 2 will not issue interrupt request. bit 12- 6 : reserved. bit 5: mc , maximum count bit. when the timer reaches its maximum count, the mc bit will set to 1 by h/w. this bit is set regardless of the en bit (66h.15). bit 4-1 : reserved. bit 0: count , continuous mode bit. set 1: timer is continuously running when timer reaches the maximum count. set 0: the en bit (66h.15) is cleared and the timer is hold after each timer count reaches the maximum count. bit 15 ? 0: tc15-tc0 , timer 2 count value. this register contains the current count of timer 2. the count is incremented by one every four internal processor clocks. bit 15- 0 : tc15 ? tc0 , timer 2 compare a value. 16.1 timer/counter unit output mode timers 0 and 1 can use one maximum count value or two maximum count value. timer 2 can use only one maximum count value. timer 0 and timer1 can be configured to single or dual maximum compare count mode, the tmrout0 or tmrout1 signals can be used to generated waveform of various duty cycle. offset : 60h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 2 count register tc15 - tc0 offset : 62h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 timer 2 maxcount compare a register tc15 - tc0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 66 maxcount a maxcount b maxcount a maxcount b dual maximum count mode single maximum count mode maxcount a 1t maxcount a 1t maxcount a * 1t:one microprocessor clock timer/counter unit output modes
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 67 17. watchdog timer R8830LV has one independent watchdog timer, which is programmable. the watchdog timer is active after reset and the timeout count with a maximum count value. the keyed sequence ( 3333h, cccch ) must be written to the register (e6h) first then writing new configuration to the watchdog timer control register. it is a single write so every one writing to watchdog timer control register must follow the rule. to read the watchdog timer control register, the keyed sequence (5555h, aaaah) must be written to the register (e6h) first. the current count should be reset before modifying the watchdog timer timeout period to ensure that an immediate timeout dose not occur. bit 15: ena , enable watchdog timer. set 1 : enable watchdog timer. set 0 : disable watchdog timer. bit 14: wrst , watchdog reset. set 1: wdt generates a system reset when wdt timeout count is reached. set 0 : wdt generates a nmi interrupt when wdt timeout count is reached if the nmiflag bit is 0. if the nmiflag bit is 1, the wdt will generate a system reset when timeout. bit 13: rstflag , reset flag. when watchdog timer reset event has occurred, hardware will set this bit to 1. this bit will be cleared by any keyed sequence write to this register or external reset. this bit is 0 after an external reset or 1 after watchdog timer reset. bit 12: nmiflag , nmi flag. after wdt generates a nmi interrupt, this bit will be set to 1 by h/w. this bit will be cleared by any keyed sequence write to this register. bit 11- 8 : reserved. bit 7- 0 : count , timeout count. the count setting determines the duration of the watchdog timer timeout interval. a. the duration equation : duration = exponent 2 / frequency b. the exponent of the count setting: (bit 7, bit 6, bit 5, bit 4, bit 3, bit 2, bit 1, bit 0) = ( exponent) ( 0 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = (n/a) ( x , x , x , x, x , x , x , x ) = ( 10 ) ( x , x , x , x, x , x , 1 , 0 ) = ( 20 ) ( x , x , x , x, x , 1 , 0 , 0 ) = ( 21 ) watchdog timer control register offset : e6h 0 reset value : c080h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 nmiflag rstflag wrst ena count res
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 68 ( x , x , x , x, 1 , 0 , 0 , 0 ) = ( 22 ) ( x , x , x , 1, 0 , 0 , 0 , 0 ) = ( 23 ) ( x , x , 1 , 0, 0 , 0 , 0 , 0 ) = ( 24 ) ( x , 1 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 25 ) ( 1 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 26 ) c. watchdog timer duration reference table: frequency\exponent 10 20 21 22 23 24 25 26 20 mhz 51 us 52 ms 104 ms 209 ms 419 ms 838 ms 1.67 s 3.35 s 25 mhz 40 us 41 ms 83 ms 167 ms 335 ms 671 ms 1.34 s 2.68 s 33 mhz 30 us 31 ms 62 ms 125 ms 251 ms 503 ms 1.00 s 2.01 s 40 mhz 25 us 26 ms 52 ms 104 ms 209 ms 419 ms 838 ms 1.67 s 50 mhz 20.5 us 21 ms 41.9 ms 83.9ms 167.8 ms 335.5 ms 671 ms 1.34 s
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 69 18. asynchronous serial port R8830LV has two asynchronous serial ports, which provide the txd, rxd pins for the full duplex bi-directional data transfer and with handshaking signals cts , enrx , rts , rtr . the serial ports support : 9-bit, 8-bit or 7-bit data transfer; odd parity, even parity, or no parity; 1 stop bits; error detection; dma transfers through the serial port; multi-drop protocol (9-bit) support; double buffers for transmit and receive. the receive/transmit clock is based on the microprocessor clock. the serial port can be used in power-saved mode, but the transfer rate must be adjusted to correctly reflect the new internal operating frequency. software is programmed through the registers ,(80h, 82h, 84h, 86h, 88h ? for port 0), ( 10h,12h,14h,16h,18h ? for port 1) to configure the asynchronous serial port. 18.1 serial port flow control the two serial ports provided with two data pins (rxd and txd) and two flow control signals ( rts , rtr ). hardware flow control is enabled when the fc bit in the serial port control register is set. and the flow control signals are configured by software to support several different protocols. 18.1.1 dce/dte protocol the R8830LV can be as a dce (data communication equipment) or as a dte ( data terminal equipment). this protocol provides flow control where one serial port is receiving data and other serial port is sending data. to implement the dce device, the enrx bit should be set and the rts bit should be cleared for the associated serial port. to implement the dte device, the enrx bit should be cleared and the rts bit should be set for the associated serial port. the enrx bit and rts bit are in the register f2h. the dce/dte protocol is asymmetric interface since the dte device can not signal the dce device that is ready to receive transmit data register(84h),(14h) transmit hold register transmit shift regoster receive data register(86h),(16h) receive buffer receive shift register txd control logic control register(80h),(10h) status register(82h),(12h) baud rate divisor register(88h),(18h) interrupt request rxd internal address/data bus serial port block diagram 16 bit 8 bit 8 bit 16 bit 16 bit 8 bit 8 bit rts rtr cts enrx
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 70 data, and the dce can not send the request to send signal. the dce/dte protocol communication step: a. dte send data to dce b. rts signal is asserted by dte when data is available. c. the rts signal is interpreted by the dce device as a request to enable its receiver. d. the dce asserts the rtr signal to response that dce is ready to receive data. 18.1.2 cts/rtr protocol the serial port can be programmed as a cts/rts protocol by clearing both enrx bit and rts bit. this protocol is a symmetric interface, which provides flow control when both ports are sending and receiving data. 18.2 dma transfer to/from a serial port function dma transfers to the serial port function as destination-synchronized dma transfers. a new transfer is requested when the transmit holding register is empty. when the port is configured for dma transmits, the corresponding transmit interrupt is disabled regardless of the txie bit setting. dma transfers from the serial port function as source-synchronized dma transfers. a new transfer is requested when the receive buffer contains valid data. when the port is configured for dma receives, the corresponding receive interrupt is disabled regardless of the rxie bit setting. the dma request is generated internally when a dma channel is being used for serial port transfers. and the drq0 or drq1 are not active when a serial port dma transfers. hardware handshaking may be used in conjunction with serial port dma transfers. dce dte enrx rts rtr cts dce/dte protocol connection rts:request to send cts:clear to send rtr:ready to receive enrx:enable receiver request rtr cts cts/rtr protocol connection cts:clear to send rtr:ready to receive cts rtr
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 71 18.3 the asynchronous modes description there are 4 modes operation in the asynchronous serial port. mode1: mode 1 is the 8-bit asynchronous communications mode. each frame consists of a start bit, eight data bits and a stop bit. when parity is used, the eighth data bit becomes the parity bit. mode 2: mode 2 is used together with mode 3 for multiprocessor communications over a common serial link. in mode 2, the rx machine will not complete a reception unless the ninth data bit is a one. any character received with the ninth bit equal to zero is ignored. no flags are set, no interrupts occur and no data is transferred to receive data register. in mode 3, characters are received regardless of the state of the ninth data bit. mode 3: mode 3 is the 9-bit asynchronous communications mode. mode 3 is the same as mode 1 except that a frame contains nine data bits. the ninth data bit becomes the parity bit when the parity feature is enabled. mode 4: mode 4 is the 7-bit asynchronous communications mode. each frame consists of a start bit, seven data bits and a stop bit. parity bit is not available in mode 4. bit 15-13: dma , dma control field. these bits configure the serial port for use with dma transfers. dma control bits (bit 15, bit 14, bit 13 )b --- receive --- transmit ( 0, 0, 0 ) --- no dma --- no dma ( 0, 0, 1 ) --- dma 0 --- dma 1 ( 0, 1, 0 ) --- dma 1 --- dma 0 ( 0, 1, 1 ) --- n/a --- n/a ( 1, 0, 0 ) --- dma 0 --- no dma ( 1, 0, 1 ) --- dma 1 --- no dma ( 1, 1, 0 ) --- no dma --- dma 0 ( 1, 1, 1 ) --- no dma --- dma 1 bit 12: rsie , receive status interrupt enable. an exception occurs during data reception or error detection occur will generate an interrupt. set 1: enable the serial port 0 to generate an interrupt request. bit 11: brk , send break. set this bit to 1 , the txd pin always drives low. serial port 0 contrl register offset : 80h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dma rise brk tb8 fc txie rxie tmode rmodd evn pe mode
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 72 long break : the txd is driven low for grater than (2m+3) bit times; short break : the txd is driven low for grater than m bit times; * m= start bit + data bits number + parity bit + stop bit bit 10 : tb8 , transmit bit 8. this bit is transmitted as ninth data bit in mode 2 and mode 3. this bit is cleared after every transmission. bit 9: fc , flow control enable. set 1: enable the hardware flow control for serial port 0. set 0 : disable the hardware flow control for serial port 0. bit 8 : txie , transmitter ready interrupt enable. when the transmit holding register is empty ( thre bit in status register is set ),it will have an interrupt occurs. set 1: enable the interrupt. set 0 : disable the interrupt. bit 7: rxie, receive data ready interrupt enable. when the receiver buffer contains valid data ( rdr bit in status register is set ) , it will generate an interrupt. set 1: enable the interrupt. set 0 : disable the interrupt. bit 6 : tmode , transmit mode. set 1: enable the tx machines. set 1: disable the tx machines. bit 5: rmode , received mode. set 1: enable the rx machines. set 1: disable the rx machines. bit 4: evn, even parity. this bit is valid only when the pe bit is set. set 1: the even parity checking is enforced (even number of 1s in frame). set 0: odd parity checking is enforced (odd number of 1s in frame). bit 3: pe , parity enable. set 1 : enable the parity checking. set 0 : disable the parity checking. bit 2-0: mode , mode of operation. ( bit 2, bit 1, bit 0) mode data bits parity bits stop bits ( 0 , 0 , 1) mode 1 7 or 8 1 or 0 1 ( 0 , 1 , 0) mode 2 9 n/a 1 ( 0 , 1 , 1) mode 3 8 or 9 1 or 0 1 ( 1 , 0 , 0) mode 4 7 n/a 1
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 73 the serial port 0 status register provides information about the current status of the serial port 0. bit 15-11 : reserved. bit 10: brk1 , long break detected. this bit should be reset by software. when a long break is detected, this bit will be set high. bit 9 : brk0 , short break detected. this bit should be reset by software. when a short break is detected, this bit will be set high bit 8: rb8 , received bit 8. this bit should be reset by software. this bit contains the ninth data bit received in mode 2 and mode 3. bit 7: rdr, received data ready. read only. the received data register contains valid data , this bit is set high. this bit can only be reset by reading the serial port 0 receive register. bit 6: thre , transmit hold register empty. read only. when the transmit hold register is ready to accept data, this bit will be set. this bit will be reset when writing data to the transmit hold register. bit 5: fer , framing error detected. this bit should be reset by software. this bit is set when a framing error is detected. bit 4: oer , overrun error detected. this bit should be reset by software. this bit is set when an overrun error is detected. bit 3: per , parity error detected. this bit should be reset by software. this bit is set when a parity error ( for mode 1 and mode 3) is detected. bit 2: temt , transmitter empty. this bit is read only. when the transmit shift register is empty, this bit will be set. bit 1: hs0 , handshake signal 0. this bit is read only. this bit reflects the inverted value of the external 0 cts pin. bit 0 : reserved. bit 15-8 : reserved serial port 0 status register offset : 82h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brk1 temt hs0 res reserved brk0 rb8 rdr thre fer oer per serial port 0 transmit register offset : 84h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved tdata
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 74 bit 7- 0 : tdata, transmit data. software writes this register with data to be transmitted on the serial port 0. bit 15-8 : reserved bit 7-0: rdata , received data. the rdr bit should be read as 1 before read the rdata register to avoid reading invalid data. bit 15-0: bauddiv , baud rate divisor. the general formula for baud rate divisor is baud rate = microprocessor clock / (16 x baudiv) for example, the microprocessor clock is 22.1184mhz and the bbdiv=5 (decimal), the baud rate of serial port is 115.2k. these bits definition are same as the bits definition of register 80h these bits definition are same as the bits definition of register 82h serial port 0 receive register offset : 86h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rdata reserved serial port 0 baud rate divisor register offset : 88h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bavddiv serial port 1 contrl register offset : 10h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dma rise brk tb8 fc txie rxie tmode rmodd evn pe mode serial port 1 status register offset : 12h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 brk1 temt hs0 res reserved brk0 rb8 rdr thre fer oer per
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 75 these bits definition are same as the bits definition of register 84h these bits definition are same as the bits definition of register 86h these bits definition are same as the bits definition of register 88h serial port 1 transmit register offset : 14h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved tdata serial port 1 receive register offset : 16h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rdata reserved serial port 1 baud rate divisor register offset : 18h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 bavddiv
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 76 19. pio unit R8830LV provides 32 programmable i/o signals, which are multi-function pins with others normal function signals. software is programmed through the registers ( 7ah, 78h, 76h, 74h, 72h, 70h) to configure the multi-function pins for pio or normal function. 19.1 pio multi-function pin list table pio no. pin no. multi function reset status/pio internal resister 0 72 tmrin1 input with 10k pull-up 1 73 tmrout1 input with 10k pull-down 2 59 pcs6 /a2 input with 10k pull-up 3 60 pcs5 /a1 input with 10k pull-up 4 48 dt/ r normal operation/ input with 10k pull-up 5 49 den normal operation/ input with 10k pull-up 6 46 srdy normal operation/ input with 10k pull-down 7 22 a17 normal operation/ input with 10k pull-up 8 20 a18 normal operation/ input with 10k pull-up 9 19 a19 normal operation/ input with 10k pull-up 10 74 tmrout0 input with 10k pull-down 11 75 tmrin0 input with 10k pull-up 12 77 drq0/int5 input with 10k pull-up 13 76 drq1/int6 input with 10k pull-up 14 50 0 mcs input with 10k pull-up 15 51 1 mcs input with 10k pull-up 16 66 0 pcs input with 10k pull-up 17 65 1 pcs input with 10k pull-up d q d q oe write pdata vcc vcc for internal pull-up for internal pull-down pin "0":un-normal function normal data in read pdata microprocessor clock pio direction pio mode normal function pio data in/out pio pin operation diagram
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 77 18 63 2 pcs / 1 cts / 1 enrx input with 10k pull-up 19 62 3 pcs / 1 rts / 1 rtr input with 10k pull-up 20 3 0 rts / 0 rtr input with 10k pull-up 21 100 0 cts / 0 enrx input with 10k pull-up 22 2 txd0 input with 10k pull-down 23 1 rxd0 input with 10k pull-down 24 68 2 mcs input with 10k pull-up 25 69 3 mcs / rfsh input with 10k pull-up 26 97 uzi input with 10k pull-up 27 98 txd1 input with 10k pull-up 28 99 rxd1 input with 10k pull-up 29 96 s6/ clkdiv input with 10k pull-up 30 52 int4 input with 10k pull-up 31 54 int2 input with 10k pull-up bit 15- 0 : pdata31-pdata16 , pio data bits. these bits pdata31- pdata16 map to the pio31 ? pio16 which indicate the driven level when the pio pin as an output or reflects the external level when the pio pin as an input . bit 15- 0 : pdir 31- pdir16 , pio direction register. set 1: configure the pio pin as an input. set 0: configure the pio pin as an output or as normal pin function. bit 15-0: pmode31-pmode16 , pio mode bit. offset : 7ah 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdata (31 - 16) pio data 1 register offset : 78h 0 reset value : ffffh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdir (31 - 16) pio direction 1 register offset : 76h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pmode (31 - 16) pio mode 1 register
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 78 the definition of pio pins are configured by the combination of pio mode and pio direction. and the pio pin is programmed individual. the definition (pio mode, pio direction) for pio pin function: ( 0 , 0 ) ? normal operation , ( 0 , 1 ) ? pio input with pull-up/pull-down ( 1 , 0 ) ? pio output , ( 1 , 1 ) -- pio input without pull-up/pull-down bit 15- 0 : pdata15- pdata0 : pio data bus. these bits pdata15- pdata0 map to the pio15 ? pio0 which indicate the driven level when the pio pin as an output or reflects the external level when the pio pin as an input. bit 15- 0 : pdir 15- pdir0 , pio direction register. set 1: configure the pio pin as an input. set 0: configure the pio pin as an output or as normal pin function. bit 15-0: pmode15-pmode0 , pio mode bit. offset : 74h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdata (15 - 0) pio data 0 register offset : 72h 0 reset value : ffffh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pdir (15 - 0) pio direction 0 register offset : 70h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pmode (15 - 0) pio mode 0 register
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 79 20. psram control unit the psram interface is provided by the R8830LV and the refresh control unit automatically generates refresh bus cycles. the refresh control unit uses the internal microprocessor clock as a operating source clock. if the power-saved mode is enabled, the refresh control unit must be programmed to reflect the new clock rate. software programs the registers (e0, e2, e4) to control the refresh control unit operation. bit 15-9 : m6-m0, refresh base. m6-m0 map to a19-a13 of the 20-bit memory refresh address. bit 8- 0 : reserved. bit 15- 9 : reserved bit 8-0: rc8-rc0, refresh counter reload value. bit 15: e , enable rcu. set 1: enable the refresh counter unit set 0 : disable the refresh counter unit. bit 14- 9 : reserved bit 8-0: t8-t0 , refresh count. read only bits and these bits present value of the down counter which triggers refresh requests. memory partition register offset : e0h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 m6 - m0 0 0 0 0 0 0 0 0 0 clock prescaler register offset : e2h 0 reset value : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 rc8 - rc0 enable rcu register offset : e4h 0 reset value : 0000h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 e t8 - t0
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 80 21. instuction set opcodes and clock cycles function format clocks notes data transfer instructions mov = move register to register/memory 1000100w mod reg r/m 1/1 register/memory to register 1000101w mod reg r/m 1/6 immediate to register/memory 1100011w mod 000 r/m data data if w=1 1/1 immediate to register 1011w reg data data if w=1 1 memory to accumulator 1010000w addr-low addr-high 6 accumulator to memory 1010001w addr-low addr-high 1 register/memory to segment register 10001110 mod 0 reg r/m 3/8 segment register to register/memory 10001100 mod 0 reg r/m 2/2 push = push memory 11111111 mod 110 r/m 8 register 01010 reg 3 segment register 000reg110 2 immediate 011010s0 data data if s=0 1 pop = pop memory 10001111 mod 000 r/m 8 register 01011 reg 6 segment register 000 reg 111 ( reg ? 01) 8 pusha = push all 01100000 36 popa = pop all 01100001 44 xchg = exchange register/memory 1000011w mod reg r/m 3/8 register with accumulator 10010 reg 3 xtal = translate byte to al 11010111 10 in = input from fixed port 1110010w port 12 variable port 1110110w 12 out = output from fixed port 1110010w port 12 variable port 1110110w 12 lea = load ea to register 10001101 mod reg r/m 1 lds = load pointer to ds 11000101 mod reg r/m (mod ? 11) 14 les = load pointer to es 11000100 mod reg r/m (mod ? 11) 14 enter = build stack frame 11001000 data-low data-high l l = 0 7 l = 1 11 l > 1 11+10(l-1) leave = tear down stack frame 11001001 7 lahf = load ah with flags 10011111 2 sahf = store ah into flags 10011110 2 pushf = push flags 10011100 2 popf = pop flags 10011101 11 arithmetic instructions add = add reg/memory with register to either 000000dw mod reg r/m 1/7 immediate to register/memory 100000sw mod 000 r/m data data if sw=01 1/8 immediate to accumulator 0000010w data data if w=1 1
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 81 function format clocks notes adc = add with carry reg/memory with register to either 000100dw mod reg r/m 1/7 immediate to register/memory 100000sw mod 010 r/m data data if sw=01 1/8 immediate to accumulator 0001010w data data if w=1 1 inc = increment register/memory 1111111w mod 000 r/m 1/8 register 01000 reg 1 sub = subtract reg/memory with register to either 001010dw mod reg r/m 1/7 immediate from register/memory 100000sw mod 101 r/m data data if sw=01 1/8 immediate from accumulator 0001110w data data if w=1 1 sbb = subtract with borrow reg/memory with register to either 000110dw mod reg r/m 1/7 immediate from register/memory 100000sw mod 011 r/m 1/8 immediate from accumulator 0001110w data data if w=1 1 dec = decrement register/memory 1111111w mod 001 r/m 1/8 register 01001 reg 1 neg = change sign register/memory 1111011w mod reg r/m 1/8 cmp = compare register/memory with register 0011101w mod reg r/m 1/7 register with register/memory 0011100w mod reg r/m 1/7 immediate with register/memory 100000sw mod 111 r/m data data if sw=01 1/7 immediate with accumulator 0011110w data data if w=1 1 mul = multiply (unsigned) 1111011w mod 100 r/m register-byte 13 register-word 21 memory-byte 18 memory-word 26 imul = integer multiply (signed) 1111011w mod 101 r/m register-byte 16 register-word 24 memory-byte 21 memory-word 29 register/memory multiply immediate (signed) 011010s1 mod reg r/m data data if s=0 23/28 div = divide (unsigned) 1111011w mod 110 r/m register-byte 18 register-word 26 memory-byte 23 memory-word 31 idiv = integer divide (signed) 1111011w mod 111 r/m register-byte 18 register-word 26 memory-byte 23 memory-word 31 aas = ascii adjust for subtraction 00111111 3 das = decimal adjust for subtraction 00101111 2 aaa = ascii adjust for addition 00110111 3 daa = decimal adjust for addition 00100111 2 aad = ascii adjust for divide 11010101 00001010 14 aam = ascii adjust for multiply 11010100 00001010 15 cbw = corrvert byte to word 10011000 2 cwd = convert word to double-word 10011001 2
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 82 function format clocks notes bit manipulation instructuions not = invert register/memory 1111011w mod 010 r/m 1/7 and = and reg/memory and register to either 001000dw mod reg r/m 1/7 immediate to register/memory 1000000w mod 100 r/m data data if w=1 1/8 immediate to accumulator 0010010w data data if w=1 1 or = or reg/memory and register to either 000010dw mod reg r/m 1/7 immediate to register/memory 1000000w mod 001 r/m data data if w=1 1/8 immediate to accumulator 0000110w data data if w=1 1 xor = exclusive or reg/memory and register to either 001100dw mod reg r/m 1/7 immediate to register/memory 1000000w mod 110 r/m data data if w=1 1/8 immediate to accumulator 0011010w data data if w=1 1 test = and function to flags , no result register/memory and register 1000010w mod reg r/m 1/7 immediate data and register/memory 1111011w mod 000 r/m data data if w=1 1/8 immediate data and accumulator 1010100w data data if w=1 1 sifts/rotates register/memory by 1 1101000w mod ttt r/m 2/8 register/memory by cl 1101001w mod ttt r/m 1+n / 7+n register/memory by count 1100000w mod ttt r/m count 1+n / 7+n string manipulation instructions movs = move byte/word 1010010w 13 ins = input byte/word from dx port 0110110w 13 outs = output byte/word to dx port 0110111w 13 cmps = compare byte/word 1010011w 18 scas = scan byte/word 101011w 13 lods = load byte/word to al/ax 1010110w 13 stos = store byte/word from al/ax 1010101w 7 repeated by count in cx: movs = move byte/word 11110010 1010010w 4+9n ins = input byte/word from dx port 11110010 0110110w 5+9n outs = output byte/word to dx port 11110010 0110111w 5+9n cmps = compare byte/word 1111011z 1010011w 4+18n scas = scan byte/word 1111001z 1010111w 4+13n lods = load byte/word to al/ax 11110010 0101001w 3+9n stos = store byte/word from al/ax 11110100 0101001w 4+3n program transfer instructions conditional transfers ?x jump if: je/jz = equal/zero 01110100 disp 1/9 jl/jnge = less/not greater or equal 01111100 disp 1/9 jle/jng = less or equal/not greater 01111110 disp 1/9 jc/jb/jnae = carry/below/not above or equal 01110010 disp 1/9 jbe/jna = below or equal/not above 01110110 disp 1/9 jp/jpe = parity/parity even 01111010 disp 1/9 jo = overflow 01110000 disp 1/9 js = sign 01111000 disp 1/9 jne/jnz = not equal/not zero 01110101 disp 1/9 jnl/jge = not less/greater or equal 01111101 disp 1/9 jnle/jg = not less or equal/greater 01111111 disp 1/9 jnc/jnb/jae = not carry/not below 01110011 disp 1/9 /above or equal jnbe/ja = not below or equal/above 01110111 disp 1/9 jnp/jpo = not parity/parity odd 01111011 disp 1/9 jno = not overflow 01110001 disp 1/9
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 83 jns = not sign 01111001 disp 1/9 function format clocks notes unconditional transfers call = call procedure direct within segment 11101000 disp-low disp-high 11 reg/memory indirect within segment 11111111 mod 010 r/m 12/17 indirect intersegment 11111111 mod 011 r/m (mod ? 11) 25 direct intersegment 10011010 segment offset 18 selector ret = retum from procedure within segment 11000011 16 within segment adding immed to sp 11000010 data-low data-high 16 intersegment 11001011 23 instersegment adding immed to sp 1001010 data-low data-high 23 jmp = unconditional jump short/long 11101011 disp-low 9/9 direct within segment 11101001 disp-low disp-high 9 reg/memory indirect within segment 11111111 mod 100 r/m 11/16 indirect intersegment 11111111 mod 101 r/m (mod ?11) 18 direct intersegment 11101010 segment offset 11 selector iteration control loop = loop cx times 11100010 disp 7/16 loopz/loope = loop while zero/equal 11100001 disp 7/16 loopnz/loopne = loop while not zero/equal 11100000 disp 7/16 jcxz = jump if cx = zero 11100011 disp 7/15 interrupt int = interrupt type specified 11001101 type 41 type 3 11001100 41 into = interrupt on overflow 11001110 43/4 bound = detect value out of range 01100010 mod reg r/m 21-60 iret = interrupt return 11001111 31 processor control instructions clc = clear carry 11111000 2 cmc = complement carry 11110101 2 stc = set carry 11111001 2 cld = clear direction 11111100 2 std = set direction 11111101 2 cli = clear interrupt 11111010 5 sti = set interrupt 11111011 5 hlt = halt 11110100 1 wait = wait 10011011 1 lock = bus lock prefix 11110000 1 esc = math coprocessor escape 11011mmm mod ppp r/m 1 nop = no operation 10010000 1 segment override prefix cs 00101110 2 ss 00110110 2 ds 00111110 2 es 00100110 2
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 84 21.1 R8830LV execution timings the above instruction timing represent the minimum execution time in clock cycles for each instruction. the timings given are based on the following assumptions: 1. the opcode, along with and data or displacement required for execution, has been prefetched and resides in the instruction queue at the time is needed. 2. no wait states or bus holds occur. 3. all word -data is located on even-address boundaries. 4. one risc micro operation( u op) maps one cycle(according the pipeline stages described below) , except the following case: 4.1 memory read u op need 6 cycles for bus. 4.2 memory push u op need 1 cycle if it has no previous memory push u op, and 5 cycles if it has previous memory push or memory write u op. 4.3 mul u op and div of alu function u op for 8 bits operation need both 8 cycles, for 16 bits operation need both 16 cycles. 4.4 all jumps, calls, ret and loopxx instructions required to fetch the next instruction for the destination address( unconditional fetch u op) will need 9 cycles. note : o p_r : operand read stage, e a : calculate effective address stage, i dle : bus idle stage, t 0 ..t3 : bus t0 ..t3 stage, a ccess : access data from cache memory stage. pipeline stages for single micro operation(one cycle): f etch d ecode o p_r a lu w b (for alu function u op) f etch d ecode e a a ccess w b (for memory function u op) pipeline stages for memory read u op (6 cycles): f etch d ecode e a a ccess i dle t 0 t 1 t 2 t 3 w b bus cycle pipeline stages for memory push u op after memory push u op (another 5 cycles): f etch d ecode e a a ccess i dle t 0 t 1 t 2 t 3 w b (1 st memory push u op) (2 nd u op) f etch d ecode e a a ccess a ccess a ccess a ccess a ccess i dle t 0 t 1 t 2 t 3 w b pipeline stall pipeline stages for unconditional fetch: f etch d ecode e a a ccess i dle t 0 t 1 t 2 t 3 f etch ( fetch u op) ( next u op) f etch d ecode e a a ccess a ccess a ccess a ccess a ccess i dle t 0 t 1 t 2 t 3 w b will be flushed these 9 cycles caused branch penalty f etch d ecode following s tages.. . (new u op)
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 85 22. dc characteristics absolute maximum rating symbol rating commercial unit note vterm terminal voltage with respect to gnd -0.5 to vcc+0.5 v v ta operating temperature 0 to +70 centigrade pt power dissipation 1.5 w recommended dc operating conditions symbol parameter min. typ. max. unit vcc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v vih input high voltage(1) 2.0 --- vcc+0.5 v vih1 input high voltage(res) 2.5 vcc+0.5 v vih2 input high voltage (x1) 2.5 vcc+0.5 v vil input low voltage -0.5 0 0.8 v note 1: rst ,x1 pins not included dc electrical characteristics symbol parameter test condition min max unit ili input leakage current (for 32 pio pins) vcc=vmax vin=gnd to vcc 300 ua ili input leakage current (others) vcc=vmax vin=gnd to vcc 80 ua ilo output leakage current vcc=vmax vin=gnd to vcc 300 ua vol output low voltage iol=2ma, vcc=min. _____ 0.4 v voh output high voltagr ioh=-2.4ma, vcc=min. 2.4 ____ v note1 :vmax=3.6v vmin=3.0v
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 86 dc electrical characteristics symbol parameter test condition min max unit note icc max operating current vcc=3.6v, 33mhz --- 85 ma fmax max operation clock frequency 5 33 mhz vcc+-5% fmax max operation clock frequency 5 25 mhz vcc+-10%
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 87 23.ac characteristics clkouta a19:a0 s6 ad15:ad0 ale bhe den dtr uzi t1 t2 t3 t4 address data ucs,lcs s2:s0 tw status read cycle pcs x, mcs x address rd 2 1 3 4 5 6 7 8 9 10 12 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 88 no. description min max unit 1 clkouta high to a address valid 0 15 ns 2 a address valid to rd low 1.5t-12 ns 3 s6 active delay 0 20 ns 4 s6 inactive delay 0 20 ns 5 ad address valid delay 0 20 ns 6 address hold 0 12 ns 7 data in setup 10 ns 8 data in hold 3 ns 9 ale active delay 0 20 ns 10 ale inactive delay 0 20 ns 11 address valid after ale inactive 1/2t-10 ns 12 ale width t-10 ns 13 rd active delay 0 15 ns 14 rd pulse width 2t-15 ns 15 rd inactive delay 0 20 ns 16 clkouta high to lcs ucs valid 0 20 ns 17 ucs,lcs inactive delay 0 20 ns 18 pcs , mcs active delay 0 20 ns 19 pcs , mcs inactive delay 0 20 ns 20 den active delay 0 20 ns 21 den inactive delay 0 20 ns 22 dtr active delay 0 20 ns 23 dtr inactive delay 0 20 ns 24 status active delay 0 20 ns 25 status inactive delay 0 20 ns 26 uzi active delay 0 20 ns 27 uzi inactive delay 0 20 ns 1. t means a clock period time 2. all timing parameters are measured at 1.5v with 50 pf loading on clkouta . all output test conditions are with cl=50 pf
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 89 clkouta a19:a0 s6 ad15:ad0 ale wr bhe den dtr uzi t1 t2 t3 t4 address data ucs,lcs s2:s0 tw status write cycle pcs x, mcs x address whb,wlb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 90 no. description min max unit 1 clkouta high to a address valid 0 15 ns 2 a address valid to wr low 1.5t-12 ns 3 s6 active delay 0 20 ns 4 s6 inactive delay 0 20 ns 5 ad address valid delay 0 15 ns 6 address hold ns 7 ale active delay 0 20 ns 8 ale width t-10 ns 9 ale inactive delay 0 20 ns 10 address valid after ale inactive 1/2t-10 ns 11 wr active delay 0 15 ns 12 wr pulse width 2t-15 ns 13 wr inactive delay 0 15 ns 14 whb , wlb active delay 0 20 ns 15 whb , wlb inactive delay 0 20 ns 16 bhe active delay 0 20 ns 17 bhe inactive delay 0 20 ns 18 clkouta high to ucs , lcs valid 0 20 ns 19 ucs , lcs inactive delay 0 20 ns 20 pcs , mcs active delay 0 20 ns 21 pcs , mcs inactive delay 0 20 ns 22 den active delay 0 20 ns 23 den inactive delay 0 20 ns 24 dtr active delay 0 20 ns 25 dtr inactive delay 0 20 ns 26 status active delay 0 20 ns 27 status inactive delay 0 20 ns 28 uzi active delay 0 20 ns 29 uzi inactive delay 0 20 ns
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 91 * the source-synchronized transfer is not followed immediately by another dma transfer no. description min max unit 1 drq is confirmed time 0 10 ns clkouta a19:a0 ad15:ad0 ale rd wr wlb whb ucs s2:s0 s6 drq0 dma (1) d00c0 c0000 20000 0 101fc 0 2211 0 2211 * 1fc * 7 5 7 6 7 6 den dt/r 1 t1 t2 t3 t4 t1 t2 t3 t4 t1
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 92 * the source-synchronized transfer is followed immediately by another dma transfer no. description min max unit 1 drq is confirmed time 0 3 ns clkouta a19:a0 ad15:ad0 ale rd wr wlb whb ucs s2:s0 s6 drq0 dma (2) c0000 c0002 20002 0 5 6 5 6 den 20000 * * 101fc 2211 0 2211 2 4433 2 4433 1fc 7 7 7 7 6 dt/r 1 t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 t1
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 93 no. description min max unit 1 hold setup time 0 10 ns 2 hlda valid delay 0 20 ns 3 hold hold time 0 3 ns 4 hlda valid delay 0 20 ns clkouta a19:a0 ad15:ad0 ale rd wr wlb ucs s2:s0 hlda hold/hlda timing ffff4 zzzzz f0 4 den ffff6 4 hold fff* f0000 fff6 0 fff6 0 b8 7 7 z 7 4 dt/r t1 t2 t3 tw tw tw t4 ti ti ti ti ti ti ti ti ti ti ti ti t1 1 2 3 4
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 94 no. description min max unit 1 ardy resolution transition setup time 0 10 ns 2 ardy active hold time 0 10 ns clkouta ale ardy srdy ardy timing lcs t1 t2 t3 tw tw tw tw tw tw t4 t1 1 2
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 95 no. description min max unit 1 srdy transition setup time 0 10 ns 2 srdy transition hold time 0 3 ns clkouta ale ardy srdy srdy timing lcs t1 t2 t3 tw tw tw tw tw t4 t1 1 2
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 96 24. package information (pqfp) 0.089 c seating plane 0.25 min a1 0.22/0.38 b1 b 0.22/0.30/0.33 0.13/0.23 0.13/0.17 c1 c with plating base metal "a" d1 20.00 0.10 d 23.20 0.25 e1 14.00 0.10 e 17.20 0.25 "a" 0.65 bsc 0~7 1.60 ref 0.25 0.88 0.15 l l1 a2 2.75 0.12 detail a 3.40 max 7 typ 15 typ detail a
rdc ? ri sc dsp controller R8830LV rdc semiconductor co. rev :1.0 subject to change without notice 97 (lqfp) sealing plane 1 25 26 50 51 75 76 100 0.127(typ) "a" 0.076(max) 0.50(typ) 1.60(max) 1.00(ref) 0.2s(typ) gauge plane 16.00 0.10 14.00 0.10 16.00 0.10 14.00 0.10 1.40 0.05 0.10 0.05 0.22 0.05 0.60 0.15 0 ~ 7 unit:mm

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